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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. document no. u19201ej3v0ud00 (3rd edition) date published november 2009 n user?s manual v850e/sj3-h, v850e/sk3-h 32-bit single-chip microcontrollers hardware 2008 v850e/sj3-h: pd70f3474 pd70f3475 pd70f3476 pd70f3477 pd70f3478 pd70f3479 pd70f3931 pd70f3932 pd70f3933 pd70f3934 pd70f3935 pd70f3936 pd70f3937 pd70f3938 pd70f3939 v850e/sk3-h: pd70f3480 pd70f3481 pd70f3482 pd70f3486 pd70f3487 pd70f3488 pd70f3925 pd70f3926 pd70f3927 user?s manual u19201ej3v0ud 2 [memo] user?s manual u19201ej3v0ud 3 notes for cmos devices (1) voltage application waveform at input pin: wa veform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cm os device stays in the ar ea between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the i nput level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input le vel may be generated due to noise, etc., causing malfunction. cmos devices behave differently t han bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fiel d, when exposed to a mos dev ice, can cause destruction of the gate oxide and ultimately degr ade the device operation. steps mu st be taken to stop generation of static electricity as much as possible, and quickly dissi pate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electric ity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operat or should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not nece ssarily define the initial st atus of a mos device. immediately after the power source is turned on, devic es with reset functions have not yet been initialized. hence, power-on does not guar antee output pin levels, i/o settings or cont ents of registers. a device is not initialized until the reset signal is received. a rese t operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device t hat uses different power supplies for the internal operation and external interface, as a rule, switch on t he external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal element s of the device, causing malfuncti on and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related spec ifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abno rmal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power o ff state must be judged separately for each device and according to related s pecifications gover ning the device. user?s manual u19201ej3v0ud 4 caution: this product uses superflash ? technology licensed from silicon storage technology, inc. iecube is a registered trademark of nec el ectronics corporation in japan and germany. minicube is a registered tradem ark of nec electronics corporati on in japan and germany or a trademark in the united states of america. eeprom, iebus, and inter equipment bus are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. superflash is a registered trademark of silicon st orage technology, inc. in several countries including the united states and japan. ? the information in this document is curr ent as of september, 2009. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec el ectronics data sheets or data books, etc., for the most up-to-date specifications of nec el ectronics products. not all products and/or types are av ailable in every country. please check with a n nec electronics sales representative for av ailability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the pr ior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. ? nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights o f third parties by or arising from the use of nec electronics pr oducts listed in this document or any other liability arising fro m the use of such products. no licens e, express, implied or otherwise, is granted under any patents, copyrights or other intellectua l property rights of nec electronics or others. ? descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and app lication examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third par ties arising from the use of these circuits, software and information. ? while nec electronics endeavors to enhance the quality, reliab ility and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to mini mize risks of damage to property or injury (including death) to persons arising from def ects in nec electronics products, cust omers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. ? nec electronics products are cl assified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a cu stomer-designated "quality assurance program" for a specific app lication. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. custom ers must check the quality grade of each ne c electronics product before using it in a particular application. "standard": computers, office equipm ent, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, ma chine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control system s, anti-disaster systems, anti- crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipmen t, submersible repeaters, nuclear reacto r control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expre ssly specified in nec electronics data sheets or data books, etc. if customers wish to use nec elec tronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note 1) "nec electronics" as used in th is statement means nec electronics corpor ation and also includes its majority-owned subsidiaries. (note 2) "nec electronics products" m eans any product developed or manufactured by or for nec electronics (as defined above). (m8e0909) user?s manual u19201ej3v0ud 5 preface readers this manual is intended for users who wish to understand the functions of the v850e/sj3-h and v850e/sk3-h and des ign application systems using the v850e/sj3-h and v850e/sk3-h. purpose this manual is intended to give users an understanding of the har dware functions of the v850e/sj3-h and v850e/sk3-h shown in the organization below. organization the manual of these products is divided into two volumes: hardware (this volume) and architecture ( v850e1 architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. caution the application examples in th is manual apply to ?standard? quality grade products for general electr onic systems. when using an example in this manual for an app lication that requires a ?special? quality grade product, thoroughly evalua te the component and circuit to be actually used to see if they satisfy the special quality grade. to understand the overall functions of the v850e/sj3-h and v850e/sk3-h read this manual according to the contents . to find the details of a regi ster where the name is known use appendix b register index . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defi ned as a reserved word in the device file. to understand the details of an instruction function refer to the v850e1 architecture user?s manual available separately. to know the electrical specificati ons of the v850e/sj3-h and v850e/sk3-h see chapter 35 electrical specifications . the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx. yyy? is described as is in a program, however, the compiler/assembler cannot recognize it correctly. user?s manual u19201ej3v0ud 6 the mark user?s manual u19201ej3v0ud 7 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850e/sj3-h, v850e/sk3-h document name document no. v850e1 architecture user?s manual u14559e v850e/sj3-h, v850e/sk3-h hardwa re user?s manual this manual documents related to development tools document name document no. ie-v850e1-cd-nw (pcmcia card ty pe on-chip debug emulator) u16647e qb-v850esx3h (in-circuit emulator) to be prepared qb-v850mini (on-chip debug emulator) u17638e qb-mini2 (on-chip debug emulator with programming function) u18371e qb-programmer programming gui operation u18527e operation u18512e c language u18513e assembly language u18514e ca850 ver. 3.20 c compiler package link directives u18515e pm+ ver. 6.30 project manager u18416e id850qb ver. 3.40 integrated debugger operation u18604e tw850 ver. 2.00 performance analysis tuning tool u17241e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 real-time os task debugger u17420e basics u18165e in-structure u18164e rx850 pro ver. 3.21 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp5 flash memory programmer u18865e user?s manual u19201ej3v0ud 8 contents chapter 1 introduction ...................................................................................................... .......... 22 1.1 general ........................................................................................................................ ...............22 1.2 features ....................................................................................................................... ..............25 1.3 application fields ............................................................................................................. ........27 1.4 ordering information ........................................................................................................... .....28 1.4.1 v850e/s j3-h.................................................................................................................... ...........28 1.4.2 v850e/ sk3-h .................................................................................................................... ..........29 1.5 pin configuration (top vi ew)................................................................................................... 29 1.5.1 v850e/s j3-h.................................................................................................................... ...........29 1.5.2 v850e/ sk3-h .................................................................................................................... ..........32 1.6 function block configuration............................................. .....................................................3 5 1.6.1 internal bl ock di agram ......................................................................................................... ........35 1.6.2 internal units ................................................................................................................. ...............39 chapter 2 pin functio ns .................................................................................................... ........... 43 2.1 list of pin functions.......................................................................................................... .......43 2.2 port sharing of alternate functions ............................... ........................................................60 2.3 pin states ..................................................................................................................... ..............65 2.4 pin i/o circuit types, i/o buffer power suppli es and connection of unused pins...........66 2.5 cautions ....................................................................................................................... ..............73 chapter 3 cpu functio n ..................................................................................................... ........... 74 3.1 features ....................................................................................................................... ..............74 3.2 cpu register set............................................................................................................... ........75 3.2.1 program regi ster set ........................................................................................................... .........76 3.2.2 system regi ster set............................................................................................................ ..........77 3.3 operation modes ................................................................................................................ .......84 3.3.1 specifying oper ation mode ...................................................................................................... ....84 3.4 address space .................................................................................................................. ........85 3.4.1 cpu address space.............................................................................................................. .......85 3.4.2 wraparound of cpu addr ess spac e ............................................................................................86 3.4.3 memory map..................................................................................................................... ...........87 3.4.4 areas .......................................................................................................................... .................91 3.4.5 recommended use of address s pace .......................................................................................100 3.4.6 peripheral i/o regist ers....................................................................................................... .......104 3.4.7 programmable peripheral i/o regist ers......................................................................................123 3.4.8 special r egister s .............................................................................................................. ..........124 3.4.9 cauti ons ....................................................................................................................... .............128 chapter 4 port functio ns ................................................................................................... ...... 133 4.1 features ....................................................................................................................... ............133 4.1.1 v850e/s j3-h.................................................................................................................... .........133 4.1.2 v850e/ sk3-h .................................................................................................................... ........133 4.2 basic port configuration....................................................................................................... .134 user?s manual u19201ej3v0ud 9 4.2.1 v850e/s j3-h.................................................................................................................... ......... 134 4.2.2 v850e/ sk3-h .................................................................................................................... ........ 135 4.3 port configuration ......................................................... .................................................... .....136 4.3.1 port 0......................................................................................................................... ................ 141 4.3.2 port 1......................................................................................................................... ................ 145 4.3.3 port 2 (v850e/ sk3-h only) ...................................................................................................... . 146 4.3.4 port 3......................................................................................................................... ................ 148 4.3.5 port 4......................................................................................................................... ................ 157 4.3.6 port 5......................................................................................................................... ................ 161 4.3.7 port 6......................................................................................................................... ................ 167 4.3.8 port 7......................................................................................................................... ................ 175 4.3.9 port 8......................................................................................................................... ................ 177 4.3.10 port 9......................................................................................................................... ................ 182 4.3.11 port 13 (v850e/ sk3-h only) ..................................................................................................... . 190 4.3.12 port 14 (v850e/ sk3-h only) ..................................................................................................... . 191 4.3.13 port 15 (v850e/ sk3-h only) ..................................................................................................... . 192 4.3.14 port cd ........................................................................................................................ ............. 194 4.3.15 port cm ........................................................................................................................ ............. 196 4.3.16 port cs........................................................................................................................ .............. 198 4.3.17 port ct........................................................................................................................ .............. 200 4.3.18 port dh ........................................................................................................................ ............. 202 4.3.19 port dl ........................................................................................................................ .............. 204 4.4 block diagrams................................................................................................................. ......207 4.5 port register settings when alternate function is used ..................................................270 4.6 cautions....................................................................................................................... ............284 4.6.1 cautions on se tting port pins .................................................................................................. ... 284 4.6.2 cautions on bit manipulation instru ction for port n r egister (pn) ................................................ 287 4.6.3 cautions on on-ch ip debug pi ns ................................................................................................ 2 88 4.6.4 cautions on p05/in tp2/drst pin ............................................................................................ 288 4.6.5 cautions on p53 pin when power is tu rned on .......................................................................... 288 4.6.6 hysteresis char acterist ics..................................................................................................... ..... 288 4.6.7 cautions on separ ate bus mode................................................................................................ 28 9 4.6.8 cautions on reading port n registers (pn: n = 3 to 5, 8) (v 850e/sj3-h only) ............................ 289 4.6.9 cautions on setting port n mode control r egisters (pmcn: n = 3 to 5, 8) ................................... 289 chapter 5 bus control function.............................. .............................................................2 90 5.1 features ....................................................................................................................... ............290 5.2 bus control pins............................................................................................................... ......291 5.2.1 pin status when internal rom, internal ra m, on-chip peripheral i/o, or expanded internal ram is a ccessed................................................................................................................ ....... 292 5.2.2 pin status in eac h operation mode ............................................................................................ 29 2 5.3 memory block function .........................................................................................................2 93 5.3.1 chip select c ontrol f unction ................................................................................................... .... 296 5.4 external bus interface mode control function ......... ..........................................................301 5.5 bus access..................................................................................................................... .........302 5.5.1 number of clo cks for a ccess .................................................................................................... . 302 5.5.2 bus size setti ng func tion...................................................................................................... ...... 303 5.5.3 access by bus si ze............................................................................................................. ....... 304 user?s manual u19201ej3v0ud 10 5.6 wait function.................................................................................................................. .........311 5.6.1 programmable wa it func tion ..................................................................................................... .311 5.6.2 external wait func tion ......................................................................................................... .......314 5.6.3 relationship between programmabl e wait and exte rnal wa it ..................................................... 315 5.6.4 programmable address wait func tion .........................................................................................316 5.7 idle state insertion func tion.................................................................................................. 318 5.8 bus hold function .............................................................................................................. ....319 5.8.1 functional outlin e ............................................................................................................. .........319 5.8.2 bus hold pr ocedur e ............................................................................................................. ......320 5.8.3 operation in power save mode..................................................................................................3 20 5.9 bus priority ................................................................................................................... ...........321 5.10 bus timing..................................................................................................................... ..........322 chapter 6 clock generation function .................... .......................................................... 328 6.1 overview ....................................................................................................................... ...........328 6.2 clock mode ..................................................................................................................... .........329 6.2.1 clock m ode 1 ................................................................................................................... ..........332 6.2.2 clock m ode 2 ................................................................................................................... ..........335 6.2.3 clock m ode 3 ................................................................................................................... ..........338 6.2.4 clock m ode 4 ................................................................................................................... ..........341 6.2.5 clock mode setti ng ............................................................................................................. .......344 6.3 registers ...................................................................................................................... ............345 6.4 operation ...................................................................................................................... ...........355 6.4.1 operation of each cl ock ........................................................................................................ .....355 6.4.2 clock output functi on .......................................................................................................... .......356 6.4.3 procedure for setting clock generation f unction for using clock m ode 1 ....................................357 6.4.4 procedure for setting clock generation function for using clock modes 2, 3, and 4 ....................360 chapter 7 16-bit timer/event counter p (tmp) . ............................................................... 364 7.1 overview ....................................................................................................................... ...........364 7.1.1 tmp0 to tmp6 ................................................................................................................... .......364 7.1.2 tmp7 and tmp8 .................................................................................................................. .....364 7.2 functions ...................................................................................................................... ...........365 7.2.1 tmp0 to tmp6 ................................................................................................................... .......365 7.2.2 tmp7 and tmp8 .................................................................................................................. .....365 7.3 configuration.................................................................................................................. .........366 7.3.1 tmp0 to tmp6 ................................................................................................................... .......366 7.3.2 tmp7 and tmp8 .................................................................................................................. .....369 7.4 registers ...................................................................................................................... ............372 7.5 timer output operati ons........................................................................................................ 394 7.6 operation ...................................................................................................................... ...........395 7.6.1 interval timer mode (tpnmd2 to tpnmd0 bi ts = 000)............................................................... 404 7.6.2 external event count mode (tpn md2 to tpnmd0 bits = 001)................................................... 416 7.6.3 external trigger pulse output mode (tpnmd2 to tpnmd0 bits = 010) .......................................425 7.6.4 one-shot pulse output mode (tpn md2 to tpnmd0 bits = 011) ................................................ 437 7.6.5 pwm output mode (tpnmd2 to tpnmd0 bi ts = 100)................................................................ 444 7.6.6 free-running timer mode (tpnmd2 to tpnmd0 bi ts = 101) ...................................................... 453 7.6.7 pulse width measurement mode (tpn md2 to tpnmd0 bits = 110) .......................................... 471 user?s manual u19201ej3v0ud 11 7.6.8 encoder count function (onl y for tmp7 and tmp8 )................................................................... 477 7.6.9 encoder compare mode (tpmmd 3 to tpmmd0 bi ts = 1000) ................................................... 491 7.7 selector function.............................................................................................................. ......499 7.8 cautions....................................................................................................................... ............501 chapter 8 16-bit timer/event counter q (tmq) ... .............................................................502 8.1 overview ....................................................................................................................... ...........502 8.2 functions ...................................................................................................................... ...........502 8.3 configuration .................................................................................................................. ........503 8.4 registers...................................................................................................................... ............506 8.5 timer output operations ............................................. ..........................................................5 21 8.6 operation ...................................................................................................................... ...........522 8.6.1 interval timer mode (tq0md2 to tq0md0 bi ts = 000).............................................................. 530 8.6.2 external event count mode (tq0 md2 to tq0md0 bits = 001).................................................. 541 8.6.3 external trigger pulse output mode (tq0md2 to tq0md0 bits = 010) ...................................... 551 8.6.4 one-shot pulse output mode (tq0 md2 to tq0md0 bits = 011) ............................................... 564 8.6.5 pwm output mode (tq0md2 to tq0md0 bi ts = 100)............................................................... 573 8.6.6 free-running timer mode (tq0md2 to tq0md0 bi ts = 101) ..................................................... 584 8.6.7 pulse width measurement mode (tq0 md2 to tq0md0 bits = 110) ......................................... 605 8.7 selector function.............................................................................................................. ......610 8.8 cautions....................................................................................................................... ............611 chapter 9 16-bit interval timer m (tmm).......... ...................................................................612 9.1 overview ....................................................................................................................... ...........612 9.2 configuration .................................................................................................................. ........613 9.3 register....................................................................................................................... .............615 9.4 operation ...................................................................................................................... ...........616 9.4.1 interval ti mer m ode............................................................................................................ ........ 616 9.4.2 cauti ons ....................................................................................................................... ............. 620 chapter 10 watch functions ..................................... ............................................................ ...621 10.1 overview ....................................................................................................................... ...........621 10.2 configuration .................................................................................................................. ........622 10.3 prescaler 3 .................................................................................................................... ...........623 10.3.1 functi on ....................................................................................................................... ............. 623 10.3.2 configur ation .................................................................................................................. ........... 623 10.3.3 regist ers ...................................................................................................................... ............. 624 10.4 watch timer functions .......................................................................................................... 626 10.4.1 functi ons...................................................................................................................... ............. 626 10.4.2 configur ation .................................................................................................................. ........... 626 10.4.3 control r egister s.............................................................................................................. ......... 628 10.4.4 operat ion ...................................................................................................................... ............ 630 10.5 real-time counter (rtc) ... ..................................................................................................... 632 10.5.1 functi on ....................................................................................................................... ............. 632 10.5.2 configur ation .................................................................................................................. ........... 633 10.5.3 regist ers ...................................................................................................................... ............. 636 10.5.4 operat ion ...................................................................................................................... ............ 649 user?s manual u19201ej3v0ud 12 chapter 11 functions of watchdog timer 2 .. ................................................................. 661 11.1 functions ...................................................................................................................... ...........661 11.2 configuration.................................................................................................................. .........662 11.3 registers ...................................................................................................................... ............663 11.4 operation ...................................................................................................................... ...........667 chapter 12 real-time output function (rto).. ................................................................. 668 12.1 function ....................................................................................................................... ............668 12.2 configuration.................................................................................................................. .........669 12.3 registers ...................................................................................................................... ............671 12.4 operation ...................................................................................................................... ...........673 12.5 usage.......................................................................................................................... ..............674 12.6 cautions ....................................................................................................................... ............674 chapter 13 a/d converter ................................................................................................... ...... 675 13.1 overview ....................................................................................................................... ...........675 13.2 functions ...................................................................................................................... ...........675 13.3 configuration.................................................................................................................. .........676 13.4 registers ...................................................................................................................... ............679 13.5 operation ...................................................................................................................... ...........690 13.5.1 basic oper ation................................................................................................................ ..........690 13.5.2 conversion operat ion ti ming .................................................................................................... ..691 13.5.3 trigger mode ................................................................................................................... ..........692 13.5.4 operati on m ode................................................................................................................. ........694 13.5.5 power-fail co mpare mode........................................................................................................ ..698 13.6 cautions ....................................................................................................................... ............703 13.7 how to read a/d converter characteristics table .... .........................................................708 chapter 14 d/a converter ................................................................................................... ...... 712 14.1 functions ...................................................................................................................... ...........712 14.2 configuration.................................................................................................................. .........712 14.3 registers ...................................................................................................................... ............713 14.4 operation ...................................................................................................................... ...........715 14.4.1 operation in normal mode ....................................................................................................... ..715 14.4.2 operation in real-t ime output mode ...........................................................................................71 5 14.4.3 cauti ons ....................................................................................................................... .............716 chapter 15 asynchronous serial interface a (uarta) ............................................. 717 15.1 port settings of uarta0 to uarta5............................... .....................................................717 15.1.1 for v850e /sj3-h ................................................................................................................ ......717 15.1.2 for v850e /sk3-h................................................................................................................ ......719 15.2 features ....................................................................................................................... ............721 15.3 configuration.................................................................................................................. .........722 15.4 registers ...................................................................................................................... ............725 15.5 interrupt request signals ................................................... ................................................... 732 15.6 operation ...................................................................................................................... ...........733 15.6.1 data fo rmat.................................................................................................................... ............733 user?s manual u19201ej3v0ud 13 15.6.2 sbf transmission/rec eption fo rmat ........................................................................................... 735 15.6.3 sbf trans missi on ............................................................................................................... ....... 737 15.6.4 sbf rec epti on.................................................................................................................. .......... 738 15.6.5 uart trans missi on .............................................................................................................. ..... 739 15.6.6 continuous transmi ssion proc edure .......................................................................................... 740 15.6.7 uart rec eptio n................................................................................................................. ........ 742 15.6.8 reception errors............................................................................................................... ......... 743 15.6.9 parity types and operat ions .................................................................................................... ... 745 15.6.10 receive data noi se f ilter ...................................................................................................... ...... 746 15.7 dedicated baud rate generator................................... .........................................................747 15.8 cautions....................................................................................................................... ............757 chapter 16 asynchronous serial interface b (uartb) ..............................................759 16.1 features ....................................................................................................................... ............759 16.2 configuration .................................................................................................................. ........760 16.3 control registers.............................................................................................................. ......764 16.4 interrupt request signals ............................................ .......................................................... 784 16.5 control modes .................................................................................................................. .......787 16.6 operation ...................................................................................................................... ...........791 16.6.1 data fo rmat .................................................................................................................... ........... 791 16.6.2 transmit oper ation ............................................................................................................. ....... 792 16.6.3 continuous transmi ssion operat ion ........................................................................................... 795 16.6.4 receive oper ation .............................................................................................................. ....... 796 16.6.5 reception error................................................................................................................ .......... 799 16.6.6 parity types and corre sponding operat ion ................................................................................. 800 16.6.7 receive data noi se f ilter ...................................................................................................... ...... 801 16.7 dedicated baud rate generator (brg) ................... .............................................................803 16.8 control flow ................................................................................................................... .........809 16.9 cautions....................................................................................................................... ............818 chapter 17 3-wire variable-length serial i/o b (csib)................................................820 17.1 port settings of csib0 to csib5 ...........................................................................................820 17.1.1 for v850e /sj3-h ................................................................................................................ ...... 820 17.1.2 for v850e /sk3-h................................................................................................................ ...... 822 17.2 features ....................................................................................................................... ............824 17.3 configuration .................................................................................................................. ........825 17.4 registers...................................................................................................................... ............828 17.5 interrupt request signals ............................................ .......................................................... 836 17.6 operation ...................................................................................................................... ...........837 17.6.1 single transfer mode (master mode, transmi ssion m ode) ......................................................... 837 17.6.2 single transfer mode (master mode, recept ion m ode) .............................................................. 839 17.6.3 single transfer mode (master mode, transmission/rec eption m ode) ......................................... 842 17.6.4 single transfer mode (slave mode, transmi ssion m ode)............................................................ 845 17.6.5 single transfer mode (slave mode, recept ion m ode) ................................................................. 847 17.6.6 single transfer mode (slave mode, transmission/rec eption m ode) ............................................ 849 17.6.7 continuous transfer mode (master mode, transmi ssion m ode) ................................................. 851 17.6.8 continuous transfer mode (master mode, recept ion m ode) ...................................................... 854 17.6.9 continuous transfer mode (master m ode, transmission/re ception mode) ................................. 857 user?s manual u19201ej3v0ud 14 17.6.10 continuous transfer mode (slave mode, transmi ssion m ode).................................................... 861 17.6.11 continuous transfer mode (slave mode, recept ion m ode) ......................................................... 863 17.6.12 continuous transfer mode (slave m ode, transmission/re ception mode) ....................................866 17.6.13 reception error................................................................................................................ ..........870 17.6.14 clock ti ming ................................................................................................................... ............871 17.7 output pins .................................................................................................................... ..........873 17.8 baud rate generator ............................................................................................................ ..874 17.8.1 baud rate generatio n ........................................................................................................... ......876 17.9 cautions ....................................................................................................................... ............877 chapter 18 3-wire variable-length serial i/o e (csie) ............................................... 878 18.1 port setting of csie0 and csie1 ...........................................................................................878 18.1.1 v850e/sj3-h (other than pd70f3931, 70f3932, 70f3933) ...................................................878 18.1.2 v850e/ sk3-h .................................................................................................................... ........879 18.2 features ....................................................................................................................... ............880 18.3 configuration.................................................................................................................. .........881 18.4 control registers .............................................................................................................. ......885 18.5 baud rate generator n (brgn) .............................................................................................895 18.6 operation ...................................................................................................................... ...........897 18.7 how to use..................................................................................................................... ..........918 18.8 cautions ....................................................................................................................... ............925 chapter 19 i 2 c bus ......................................................................................................................... . 926 19.1 port settings of i 2 c00 to i 2 c05................................................................................................927 19.1.1 for v850e /sj3-h ................................................................................................................ ......927 19.1.2 for v850e /sk3-h................................................................................................................ ......929 19.2 features ....................................................................................................................... ............931 19.3 configuration.................................................................................................................. .........932 19.4 registers ...................................................................................................................... ............936 19.5 i 2 c bus mode functions .........................................................................................................95 4 19.5.1 pin confi guratio n.............................................................................................................. ..........954 19.6 i 2 c bus definitions and control methods ....................... ......................................................955 19.6.1 start c onditi on................................................................................................................ ............956 19.6.2 addre sses...................................................................................................................... ............957 19.6.3 transfer direction specific ation ............................................................................................... ...958 19.6.4 ack ............................................................................................................................ ...............959 19.6.5 stop condi tion................................................................................................................. ...........960 19.6.6 wait state ..................................................................................................................... .............961 19.6.7 wait state canc ellation method................................................................................................. .963 19.7 i 2 c interrupt request signals (intiicn)........................... ......................................................964 19.7.1 master devic e operat ion ........................................................................................................ ....965 19.7.2 slave device operation (when receiving slave address (addr ess matc h)) .................................968 19.7.3 slave device operation (when re ceiving extens ion c ode) .......................................................... 972 19.7.4 operation without communica tion .............................................................................................976 19.7.5 arbitration loss operation (operation as slave after arbi tration loss) ..........................................977 19.7.6 operation when arbitration loss occurs ( no communication after arbitrati on loss) .....................979 19.8 interrupt request signal (intiicn) generation ti ming and wait control .........................986 19.9 address match detection method ..... ....................................................................................987 user?s manual u19201ej3v0ud 15 19.10 error detection................................................................................................................ ........987 19.11 extension code................................................................................................................. ......988 19.12 arbitration.................................................................................................................... ............989 19.13 wakeup function ................................................................................................................ ....990 19.14 communication reservation ........................................... ......................................................991 19.14.1 when communication reservation function is enabled (iicfn.iicr svn bit = 0)......................... 991 19.14.2 when communication reservation function is disabled (iicfn.ii crsvn bit = 1) ........................ 995 19.15 cautions....................................................................................................................... ............996 19.16 communication operations...................................................................................................998 19.16.1 master operation in si ngle master system ................................................................................. 999 19.16.2 master operation in multimaste r system .................................................................................. 1000 19.16.3 slave oper ation ................................................................................................................ ....... 1003 19.17 timing of data communication.................................... .......................................................1007 chapter 20 iebus controller..................................... ........................................................... ..1014 20.1 functions ...................................................................................................................... .........1014 20.1.1 communication protoc ol of i ebus ........................................................................................... 1014 20.1.2 determination of bus mast ership (arb itrati on).......................................................................... 1015 20.1.3 communicati on m ode ............................................................................................................. 1015 20.1.4 communicati on addres s.......................................................................................................... 1015 20.1.5 broadcast comm unicati on ....................................................................................................... 1 016 20.1.6 transfer format of iebus ....................................................................................................... .. 1016 20.1.7 transfer data .................................................................................................................. ......... 1026 20.1.8 bit fo rmat..................................................................................................................... ............ 1028 20.2 configuration .................................................................................................................. ......1029 20.3 registers...................................................................................................................... ..........1031 20.4 interrupt operations of iebus cont roller ...........................................................................1061 20.4.1 interrupt cont rol bl ock........................................................................................................ ...... 1061 20.4.2 example of ident ifying in terrupt ............................................................................................... 1063 20.4.3 interrupt s ource list.......................................................................................................... ........ 1066 20.4.4 communication error sour ce processi ng list ............................................................................ 1067 20.5 interrupt request signal generation timing and main cpu processing .......................1069 20.5.1 master tr ansmissi on ............................................................................................................ .... 1069 20.5.2 master re ceptio n............................................................................................................... ....... 1071 20.5.3 slave trans missi on ............................................................................................................. ..... 1073 20.5.4 slave rec eptio n................................................................................................................ ........ 1075 20.5.5 interval of occurrence of interrupt request signal for iebus cont rol ......................................... 1077 20.6 caution........................................................................................................................ ...........1081 chapter 21 can controller ......................................... ......................................................... ..1082 21.1 overview ....................................................................................................................... .........1082 21.1.1 featur es ....................................................................................................................... ........... 1082 21.1.2 overview of func tions .......................................................................................................... .... 1083 21.1.3 configur ation .................................................................................................................. ......... 1084 21.2 can protocol................................................................................................................... ......1085 21.2.1 frame fo rmat................................................................................................................... ........ 1085 21.2.2 frame types .................................................................................................................... ........ 1086 21.2.3 data frame and re mote fr ame ................................................................................................. 108 6 user?s manual u19201ej3v0ud 16 21.2.4 error fr ame .................................................................................................................... ..........1094 21.2.5 overload frame................................................................................................................. .......1095 21.3 functions ...................................................................................................................... ........ 1096 21.3.1 determining bus prio rity....................................................................................................... ....1096 21.3.2 bit stu ffing................................................................................................................... .............1096 21.3.3 multi ma sters .................................................................................................................. .........1096 21.3.4 multi cast ..................................................................................................................... ............1096 21.3.5 can sleep mode/can st op mode func tion ..............................................................................1097 21.3.6 error contro l func tion ......................................................................................................... ......1097 21.3.7 baud rate cont rol func tion..................................................................................................... ...1104 21.4 connection with target system . ........................................................................................ 1108 21.5 internal registers of can contro ller ................................................................................. 1109 21.5.1 can controller c onfigurat ion................................................................................................... .1109 21.5.2 register a ccess ty pe ........................................................................................................... ....1110 21.5.3 register bit c onfigurat ion ..................................................................................................... ....1144 21.6 registers ...................................................................................................................... ......... 1148 21.7 bit set/clear function......................................................................................................... . 1184 21.8 can controller initializat ion ............................................................................................... 118 6 21.8.1 initialization of can m odule................................................................................................... ..1186 21.8.2 initialization of message buffer ............................................................................................... .1186 21.8.3 redefinition of message bu ffer ................................................................................................1 186 21.8.4 transition from initializati on mode to operat ion m ode.............................................................. 1187 21.8.5 resetting error counter cn erc of can module ...................................................................... 1188 21.9 message reception.............................................................................................................. 1189 21.9.1 message rec eptio n .............................................................................................................. ....1189 21.9.2 reading recept ion dat a......................................................................................................... ...1190 21.9.3 receive history list func tion .................................................................................................. ...1191 21.9.4 mask func tion .................................................................................................................. ........1193 21.9.5 multi buffer receive block func tion ...........................................................................................1 195 21.9.6 remote frame recept ion ......................................................................................................... .1196 21.10 message transmission........................................................................................................ 119 7 21.10.1 message trans missi on ........................................................................................................... ..1197 21.10.2 transmit history list func tion ................................................................................................. ...1199 21.10.3 automatic block tr ansmission ( abt)........................................................................................1201 21.10.4 transmission abor t proc ess..................................................................................................... 1203 21.10.5 remote frame transmissi on.....................................................................................................1 204 21.11 power saving modes ........................................................................................................... 12 05 21.11.1 can sleep mode ................................................................................................................. ....1205 21.11.2 can stop mode .................................................................................................................. .....1207 21.11.3 example of using pow er saving modes ...................................................................................1208 21.12 interrupt function ............................................................................................................. ... 1209 21.13 diagnosis functions and special operational mode s ..................................................... 1210 21.13.1 receive-onl y m ode.............................................................................................................. ....1210 21.13.2 single-shot mode............................................................................................................... ......1211 21.13.3 self-tes t mode ................................................................................................................. ........1212 21.13.4 transmission/reception operati on in each operat ion m ode ..................................................... 1213 21.14 time stamp function........................................................................................................... 1 214 21.14.1 time stamp functi on ............................................................................................................ ....1214 user?s manual u19201ej3v0ud 17 21.15 baud rate settings ............................................................................................................. ..1216 21.15.1 bit rate setti ng condi tions .................................................................................................... .... 1216 21.15.2 representative examples of baud rate settings ....................................................................... 1220 21.16 operation of can controller ............. ..................................................................................1224 chapter 22 dma function (dma controller) ..... .............................................................1250 22.1 features ....................................................................................................................... ..........1250 22.2 configuration .................................................................................................................. ......1251 22.3 registers...................................................................................................................... ..........1252 22.4 transfer targets............................................................. .................................................. .....1261 22.5 transfer modes ................................................................................................................. ....1261 22.6 transfer types ................................................................................................................. .....1262 22.7 dma channel priorities ........................................................................................................1 263 22.8 time related to dma transfer .................................... ........................................................1263 22.9 dma transfer start factors ......................................... ........................................................1264 22.10 dma abort factors .............................................................................................................. .1265 22.11 end of dma transfer ............................................................................................................ 1265 22.12 operation timing ............................................................................................................... ...1265 22.13 cautions....................................................................................................................... ..........1270 chapter 23 crc functio n .................................................................................................... ......1273 23.1 functions ...................................................................................................................... .........1273 23.2 configuration .................................................................................................................. ......1273 23.3 registers...................................................................................................................... ..........1274 23.4 operation ...................................................................................................................... .........1275 23.5 usage method ................................................................................................................... ....1276 chapter 24 interrupt/exception processing f unction .............................................1278 24.1 features ....................................................................................................................... ..........1278 24.2 non-maskable interrupts.................... ..................................................................................12 84 24.2.1 operat ion ...................................................................................................................... .......... 1286 24.2.2 restore........................................................................................................................ ............ 1287 24.2.3 np fl ag ........................................................................................................................ ............ 1288 24.3 maskable interrupts ............................................................................................................ ..1289 24.3.1 operat ion ...................................................................................................................... .......... 1289 24.3.2 restore........................................................................................................................ ............ 1291 24.3.3 priorities of ma skable inte rrupts .............................................................................................. 1292 24.3.4 interrupt control r egister ( xxicn)............................................................................................. . 1296 24.3.5 interrupt mask registers 0 to 6, 7l (imr0 to im r6, imr 7l)..................................................... 1300 24.3.6 in-service priority register (ispr) ............................................................................................ 1303 24.3.7 id flag........................................................................................................................ .............. 1304 24.3.8 watchdog timer mode regi ster 2 (w dtm2) ............................................................................. 1304 24.4 software exception............................................................................................................. ..1305 24.4.1 operat ion ...................................................................................................................... .......... 1305 24.4.2 restore........................................................................................................................ ............ 1306 24.4.3 ep fl ag........................................................................................................................ ............. 1307 24.5 exception trap ................................................................................................................. .....1308 24.5.1 illegal opcode definit ion ...................................................................................................... ..... 1308 user?s manual u19201ej3v0ud 18 24.5.2 debug tr ap..................................................................................................................... ..........1310 24.6 external interrupt request input pins (nmi a nd intp0 to intp9) ................................... 1312 24.6.1 noise elim inatio n .............................................................................................................. .......1312 24.6.2 edge detec tion................................................................................................................. ........1312 24.7 interrupt acknowledge time of cpu.................................................................................. 1323 24.8 periods in which interrupts are not acknowledge d by cpu.......................................... 1325 24.9 cautions ....................................................................................................................... ......... 1325 chapter 25 key interrupt function ....................... ............................................................ 1326 25.1 function ....................................................................................................................... ......... 1326 25.2 register ....................................................................................................................... .......... 1327 25.3 cautions ....................................................................................................................... ......... 1327 chapter 26 standby function ................................................................................................ 1329 26.1 overview ....................................................................................................................... ........ 1329 26.2 registers ...................................................................................................................... ......... 1330 26.3 halt mode ...................................................................................................................... ..... 1334 26.3.1 setting and operat ion st atus ................................................................................................... .1334 26.3.2 releasing ha lt m ode............................................................................................................ .1334 26.4 idle1 mode..................................................................................................................... ...... 1336 26.4.1 setting and operat ion st atus ................................................................................................... .1336 26.4.2 releasing id le1 m ode........................................................................................................... .1336 26.5 idle2 mode..................................................................................................................... ...... 1339 26.5.1 setting and operat ion st atus ................................................................................................... .1339 26.5.2 releasing id le2 m ode........................................................................................................... .1340 26.5.3 securing setup time when releasing id le2 m ode ................................................................... 1342 26.6 stop mode ...................................................................................................................... ..... 1343 26.6.1 setting and operat ion st atus ................................................................................................... .1343 26.6.2 releasing st op m ode ............................................................................................................ 1343 26.6.3 securing oscillation stabilization ti me when releasi ng stop mode .........................................1346 26.7 subclock operation mode................................................................................................... 1347 26.7.1 setting and operat ion st atus ................................................................................................... .1347 26.7.2 releasing subclock operation mode ........................................................................................1347 26.8 sub-idle mode.................................................................................................................. ... 1350 26.8.1 setting and operat ion st atus ................................................................................................... .1350 26.8.2 releasing sub- idle m ode.......................................................................................................1 351 26.9 status transition diag ram .................................................................................................. 1354 chapter 27 reset functions ................................................................................................. .. 1358 27.1 overview ....................................................................................................................... ........ 1358 27.2 registers to check reset source ................................ ...................................................... 1360 27.3 operation ...................................................................................................................... ........ 1361 27.3.1 reset operation vi a reset pin ...............................................................................................136 1 27.3.2 reset operation by watc hdog timer 2 (w dt2res) .................................................................1363 27.3.3 reset operation by low-vo ltage detector (lvir es) ................................................................. 1365 27.3.4 reset operation by clo ck monitor (c lmres) ..........................................................................1366 27.3.5 operation after reset re lease .................................................................................................. .1368 27.3.6 reset function operation flow .................................................................................................. 1369 user?s manual u19201ej3v0ud 19 chapter 28 clock monitor ......................................... .......................................................... ....1370 28.1 functions ...................................................................................................................... .........1370 28.2 configuration .................................................................................................................. ......1370 28.3 register....................................................................................................................... ...........1371 28.4 operation ...................................................................................................................... .........1372 chapter 29 low-voltage detector........................... ...........................................................1375 29.1 functions ...................................................................................................................... .........1375 29.2 configuration .................................................................................................................. ......1375 29.3 registers...................................................................................................................... ..........1376 29.4 operation ...................................................................................................................... .........1378 29.4.1 to use for internal re set signal (l vires) ................................................................................ 1378 29.4.2 to use for inte rrupt (intlvi) .................................................................................................. . 1379 29.5 ram retention voltage detection operation ......... ...........................................................1380 29.6 emulation function ............................................................................................................. .1381 chapter 30 regulator ........................................................................................................ ........1382 30.1 overview ....................................................................................................................... .........1382 30.2 operation ...................................................................................................................... .........1383 chapter 31 rom correction function .................... ...........................................................1384 31.1 overview ....................................................................................................................... .........1384 31.2 registers...................................................................................................................... ..........1385 31.3 rom correction operation and program flow.......... ........................................................1388 31.4 cautions....................................................................................................................... ..........1390 chapter 32 flash memory.................................................................................................... .....1391 32.1 features ....................................................................................................................... ..........1391 32.2 memory configuration................................... .......................................................................1 392 32.3 functional outline ............................................................................................................. ...1394 32.4 rewriting by dedicated flash memory programmer . .......................................................1397 32.4.1 programming env ironment ...................................................................................................... 13 97 32.4.2 communicati on m ode ............................................................................................................. 1398 32.4.3 flash memory cont rol........................................................................................................... ... 1406 32.4.4 selection of comm unication mode ........................................................................................... 1407 32.4.5 communication commands ..................................................................................................... 1408 32.4.6 pin connec tion................................................................................................................. ........ 1409 32.5 rewriting by self programming ........ ..................................................................................1414 32.5.1 overvi ew ....................................................................................................................... .......... 1414 32.5.2 featur es ....................................................................................................................... ........... 1415 32.5.3 standard self progr amming fl ow.............................................................................................. 141 8 32.5.4 flash f uncti ons ................................................................................................................ ........ 1419 32.5.5 pin proc essi ng................................................................................................................. ........ 1419 32.5.6 internal res ources used........................................................................................................ ... 1420 chapter 33 option byte function............................ .............................................................14 21 33.1 option byte (0000007ah).............................................. .......................................................142 2 user?s manual u19201ej3v0ud 20 33.2 option byte (0000007 bh) .................................................................................................... 1423 chapter 34 on-chip debug function ....................... ............................................................ 1425 34.1 debugging with dcu ........................................................................................................... 14 26 34.1.1 connection circui t exam ple..................................................................................................... .1426 34.1.2 interface signal s .............................................................................................................. ........1427 34.1.3 maskable f uncti ons............................................................................................................. .....1429 34.1.4 regist er ....................................................................................................................... ............1429 34.1.5 operat ion...................................................................................................................... ...........1431 34.1.6 cauti ons ....................................................................................................................... ...........1432 34.2 debugging without using dcu ........................................ .................................................. 1433 34.2.1 circuit connecti on exam ples.................................................................................................... 1433 34.2.2 maskable f uncti ons............................................................................................................. .....1435 34.2.3 securement of us er resour ces.................................................................................................14 36 32.2.4 c auti ons ............................................................................................................... ......................1443 34.3 rom security function ....................................................................................................... 144 4 34.3.1 security id .................................................................................................................... ...........1444 34.3.2 setti ng ........................................................................................................................ .............1445 chapter 35 electrical specifications ....................... ........................................................ 1447 35.1 absolute maximum ratings ................................................................................................ 1447 35.2 capacitance .................................................................................................................... ...... 1449 35.3 operating conditions .......................................................................................................... 1 449 35.4 oscillator characteristi cs.................................................................................................... 1 450 35.4.1 main clock oscillator characteri stics.........................................................................................1 450 35.4.2 subclock oscillator c haracterist ics ...........................................................................................1 453 35.4.3 pll characte ristics ............................................................................................................ ......1454 35.4.4 sscg characte ristics ........................................................................................................... ...1454 35.4.5 internal oscillator characteri stics............................................................................................ ..1454 35.5 regulator characteristics ................................................................................................... 145 5 35.6 dc characteristics ............................................................................................................. .. 1456 35.6.1 i/o level ...................................................................................................................... .............1456 35.6.2 supply cu rrent ................................................................................................................. ........1458 35.7 data retention characteristics... ........................................................................................ 1459 35.8 ac characteristics ............................................................................................................. .. 1460 35.8.1 clkout output timi ng ........................................................................................................... .1461 35.8.2 bus ti ming..................................................................................................................... ...........1462 35.9 basic operation................................................................................................................ .... 1475 35.10 flash memory programming characteristics ............. ...................................................... 1486 chapter 36 package drawings .............................................................................................. 14 88 chapter 37 recommended soldering conditions. ........................................................ 1490 appendix a development tools............................................................................................. 14 92 a.1 software package ............................................................................................................... . 1497 a.2 language processing software ......................................................................................... 1497 user?s manual u19201ej3v0ud 21 a.3 control software ............................................................................................................... ....1497 a.4 debugging tools (hardware)........................................... ....................................................1498 a.4.1 when using iecube qb-v850esx3 h.................................................................................... 1498 a.4.2 when using on-chip debug emul ator ie-v850e 1-cd-nw ....................................................... 1501 a.4.3 when using minicu be qb-v850m ini .................................................................................... 1502 a.4.4 when using minicu be2 qb-mi ni2 ........................................................................................ 1503 a.5 debugging tools (software) ............................................ ....................................................1504 a.6 embedded software .............................................................................................................1 505 a.7 flash memory writing tools................................................................................................1506 appendix b register index .................................................................................................. ......1507 appendix c instruction set list........................................................................................... .1527 c.1 conventions .................................................................................................................... ......1527 c.2 instruction set (in alphabetical order).................... ...........................................................1530 appendix d list of cautions............................................................................................... .....1537 appendix e revision history ................................................................................................ ....1592 e.1 major revisions in this edition................................... ........................................................1592 e.2 revision history of previous editions........................ ........................................................1596 user?s manual u19201ej3v0ud 22 chapter 1 introduction the v850e/sj3-h and v850e/sk3-h are the products in the nec electronics v850 single-chip microcontrollers designed for real-time control applications. 1.1 general the v850e/sj3-h and v850e/sk3-h are 32-bit single-chip microcontrollers that include the v850e1 cpu core and peripheral functions such as rom/ram, a timer/counter, seri al interfaces, an a/d converter, and a d/a converter. as for automotive lan, the v850e/sj3-h a nd v850e/sk3-h are provided with iebus tm (inter equipment bus tm ), and some of the models are also provided with can (controller area network). in addition to high real-time response characteristics a nd 1-clock-pitch basic instructions, the v850e/sj3-h and v850e/sk3-h feature multiply in structions, saturated operation instructions, bi t manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. moreover, as a real-time control system, the v850e/sj3-h and v850e/sk3-h enable extremely high cost performan ce for automotive-use multimedia equipment such as car audio systems. table 1-1 lists the products of the v850e/sj3-h and v850e/sk3-h. a model of the v850e/sj3-h and v850e/sk3-h with reduced i/o, timer/counter, and serial interface functions, v850es/sj3, is also available. see table 1-2 list of v850es/sj3 products . chapter 1 introduction user?s manual u19201ej3v0ud 23 table 1-1. v850e/sj3-h and v850e/sk3-h products (1/2) (a) v850e/sj3-h (144-pin plastic lqfp (20 20)) rom maskable interrupts function part number type size ram size (+ expanded internal ram size) operating frequency (max.) i 2 c automotive lan external internal non- maskable interrupts pd70f3474 iebus: 1 ch 94 pd70f3475 iebus/can: 1 ch 98 pd70f3476 1280 kb iebus/can: 1 ch, can: 1 ch 102 pd70f3477 iebus: 1 ch 94 pd70f3478 iebus/can: 1 ch 98 pd70f3479 1536 kb 60 kb (+ 32 kb) iebus/can: 1 ch, can: 1 ch 102 pd70f3931 iebus: 1 ch 88 pd70f3932 iebus/can: 1 ch 92 pd70f3933 512 kb 60 kb (none) iebus/can: 1 ch, can: 1 ch 96 pd70f3934 iebus: 1 ch 94 pd70f3935 iebus/can: 1 ch 98 pd70f3936 768 kb iebus/can: 1 ch, can: 1 ch 102 pd70f3937 iebus: 1 ch 94 pd70f3938 iebus/can: 1 ch 98 pd70f3939 flash memory 1024 kb 60 kb (+16 kb) 48 mhz on-chip iebus/can: 1 ch, can: 1 ch 10 102 2 remark also read caution and remark on the next page. chapter 1 introduction user?s manual u19201ej3v0ud 24 table 1-1. v850e/sj3-h and v850e/sk3-h products (2/2) (b) v850e/sk3-h (176-pin plastic lqfp (24 24)) rom maskable interrupts function part number type size ram size (+ expanded internal ram size) operating frequency (max.) i 2 c automotive lan external internal non- maskable interrupts pd70f3480 iebus: 1 ch 94 pd70f3481 iebus: 1 ch, can: 1 ch 98 pd70f3482 1536 kb iebus: 1 ch, can: 2 ch 102 pd70f3486 iebus: 1 ch 94 pd70f3487 iebus: 1 ch, can: 1 ch 98 pd70f3488 1280 kb 60 kb (+ 32 kb) iebus: 1 ch, can: 2 ch 102 pd70f3925 iebus: 1 ch 94 pd70f3926 iebus: 1 ch, can: 1 ch 98 pd70f3927 flash memory 1024 kb 60 kb (+ 16 kb) 48 mhz on-chip iebus: 1 ch, can: 2 ch 10 102 2 caution note with caution that in addition to the contents of the above table, the pd70f3931, 70f3932, and 70f3933 also differ from the other products in terms of the following functions. part number csie i 2 c pd70f3931, 70f3932, 70f3933 none 4 ch other than pd70f3931, 70f3932, and 70f3933 on-chip (2 ch) 6 ch remark the part numbers of the v850e/sj3-h and v850e/sk3-h are shown as follows in this manual. ? can controller version pd70f3475, 70f3476, 70 f3478, 70f3479, 70f3481, 70f3482, 70f3487, 70f3488, 70f3926, 70f3927, 70f3932, 70f3933, 70f3935, 70f3936, 70f3938, and 70f3939 ? can controller (2-channel) version pd70f3476, 70f3479, 70f3482, 70f3488, 70f3927, 70f3933, 70f3936, and 70f3939 ? expanded internal ram version pd70f3474, 70f3475, 70 f3476, 70f3477, 70f3478, 70f3479, 70f3480, 70f3481, 70f3482, 70f3486, 70f3487, 70f3 488, 70f3925, 70f3926, 70f3927, 70f 3934, 70f3935, 70f3936, 70f3937, 70f3938, and 70f3939 chapter 1 introduction user?s manual u19201ej3v0ud 25 table 1-2. v850es/sj3 products rom maskable interrupts function part number type size ram size operating frequency (max.) i 2 c automotive lan external internal non- maskable interrupts pd70f3344 384 kb 32 kb pd70f3345 512 kb 40 kb pd70f3346 640 kb 48 kb pd70f3347 768 kb 60 kb pd70f3348 1024 kb 60 kb iebus: 1 ch pd70f3354 384 kb 32 kb pd70f3355 512 kb 40 kb pd70f3356 640 kb 48 kb pd70f3357 768 kb 60 kb pd70f3358 1024 kb 60 kb iebus/can: 1 ch 64 pd70f3364 384 kb 32 kb pd70f3365 512 kb 40 kb pd70f3366 640 kb 48 kb pd70f3367 768 kb 60 kb pd70f3368 flash memory 1024 kb 60 kb 32 mhz on-chip iebus/can: 1 ch, can: 1 ch 9 68 2 1.2 features minimum instruction execution time: 20.8 ns (operating with 48 mhz) general-purpose registers: 32 bits 32 registers cpu features: signed multiplication (16 16 32): 1 or 2 clocks signed multiplication (32 32 64): 1 or 2 clocks saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instruction memory space: 64 mb of linear address space (for programs and data) external expansion: up to approximately 30 mb ? internal memory: ram: 60 kb (see table 1-1 ) expanded internal ram: 16/32 kb (see table 1-1 ) flash memory: 512/768/1024/1280/1536 kb (see table 1-1 ) ? external bus interface: separate bus/multiplexed bus output selectable 8-/16-bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function chapter 1 introduction user?s manual u19201ej3v0ud 26 interrupts and exceptions: non-maskable interrupts: 2 sources maskable interrupts: 98/10 2/104/106/108/112 sources (see table 1-1 ) software exceptions: 32 sources exception trap: 2 sources i/o lines: i/o ports: 128 (v850e/sj3-h) 156 (v850e/sk3-h) timer function: 16-bit interval timer m (tmm): 3 channels 16-bit timer/event counter p (tmp): 9 channels (tmp7 and tmp8 include the encoder count function) 16-bit timer/event counter q (tmq): 1 channel watch timer: 1 channel real-time counter (rtc) 1 channel watchdog timer: 1 channel real-time output port: 6 bits 2 channels serial interface: asynchronous serial interface a (uarta): 6 channels asynchronous serial interface b (uartb): 2 channels 3-wire variable length serial interface b (csib): 6 channels 3-wire variable length serial interface e (csie): 2 channels (other than pd70f3931(v850e/sj3-h), 70f39 32 (v850e/sj3-h), and 70f3933 (v850e/sj3-h)) 0 channels ( pd70f3931 (v850e/sj3-h), 70f3932 (v850e/ sj3-h), and 70f3933 (v850e/sj3-h) only) i 2 c bus interface (i 2 c): 6 channels (other than pd70f3931 (v850e/sj3-h), 70f393 2 (v850e/sj3-h), and 70f3933 (v850e/sj3-h)) 4 channels ( pd70f3931 (v850e/sj3-h), 70f3932 (v850e/ sj3-h), and 70f3933 (v850e/sj3-h) only) uarta: 1 channel uartb: 2 channels csib: 3 channels note csie: 1 channel (other than pd70f3931 (v850e/sj3-h), 70f39 32 (v850e/sj3-h), and 70f3933 (v850e/sj3-h)) 0 channels ( pd70f3931(v850e/sj3-h), 70f3932 (v850e/s j3-h), and 70f3933 (v850e/sj3-h) only) i 2 c: 2 channels (other than pd70f3931 (v850e/sj3-h), 70f393 2 (v850e/sj3-h), and 70f3933 (v850e/sj3-h)) 1 channel ( pd70f3931 (v850e/sj3-h), 70f3932 (v850e/ sj3-h), and 70f3933 (v850e/sj3-h) only) csib/i 2 c: 1 channel uarta/csib: 1 channel uarta/csie: 1 channel (other than pd70f3931 (v850e/sj3-h), 70f39 32 (v850e/sj3-h), and 70f3933 (v850e/sj3-h)) 0 channels ( pd70f3931 (v850e/sj3-h), 70f3932 (v 850e/sj3-h), and 70f3933 (v850e/sj3-h) only) uarta/ i 2 c: 2 channels note chapter 1 introduction user?s manual u19201ej3v0ud 27 uarta/csib/i 2 c: 1 channel (other than pd70f3931 (v850e/sj3-h), 70f39 32 (v850e/sj3-h), and 70f3933 (v850e/sj3-h)) 0 channels ( pd70f3931 (v850e/sj3-h), 70f3932 (v 850e/sj3-h), and 70f3933 (v850e/sj3-h) only) note these channels can also be used in the following combinations. csib: 2 channels uarta/i 2 c: 1 ch csib (reception only)/uarta/i 2 c: 1 channel caution in the v850e/sk3-h, serial in terfaces can also be used in the following combinations. uarta: 5 channels uartb: 2 channels csib: 3 channels csie: 2 channels i 2 c: 4 channels csib/i 2 c: 2 channels uarta/csib: 1 channel iebus controller: 1 channel can controller: 1/2 channels (can controller version only) a/d converter: 10-bit resolution: 16 channels d/a converter: 8-bit resolution: 2 channels dma controller: 4 channels crc function: generates 16-bit error detection code for data in 8-bit units dcu (debug control unit): jtag interface rom correction: 8 correct ion addresses specifiable clock generator: during main clock or subclock operation 7-level cpu clock (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode/sscg mode selectable clock generation function selectable by setting the option byte internal oscillation clock: 220 khz (typ.) power-save functions: halt/idle1/idle2/stop/subclock/sub-idle mode package: 144-pin plastic lqfp (fine pitch) (20 20) (v850e/sj3-h) 176-pin plastic lqfp (fine pitch) (24 24) (v850e/sk3-h) 1.3 application fields automotive-use multimedia such as car audio systems chapter 1 introduction user?s manual u19201ej3v0ud 28 1.4 ordering information 1.4.1 v850e/sj3-h part number package internal rom (flash memory) quality grade pd70f3474gja-gae-g pd70f3475gja-gae-g pd70f3476gja-gae-g 1280 kb pd70f3477gja-gae-g pd70f3478gja-gae-g pd70f3479gja-gae-g 1536 kb pd70f3931gja-gae-g pd70f3932gja-gae-g pd70f3933gja-gae-g 512 kb pd70f3934gja-gae-g pd70f3935gja-gae-g pd70f3936gja-gae-g 768 kb pd70f3937gja-gae-g pd70f3938gja-gae-g pd70f3939gja-gae-g 144-pin plastic lqfp (fine pitch) (20 20) 1024 kb (a) remark the v850e/sj3-h microcontrollers are lead-free products. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know t he specification of quality grade on the devices and its recommended applications. chapter 1 introduction user?s manual u19201ej3v0ud 29 1.4.2 v850e/sk3-h part number package internal rom (flash memory) quality grade pd70f3480gma-gar-g pd70f3481gma-gar-g pd70f3482gma-gar-g 1536 kb pd70f3486gma-gar-g pd70f3487gma-gar-g pd70f3488gma-gar-g 1280 kb pd70f3925gma-gar-g pd70f3926gma-gar-g pd70f3927gma-gar-g 176-pin plastic lqfp (fine pitch) (24 24) 1024 kb (a) remark the v850e/sk3-h microcontrollers are lead-free products. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know t he specification of quality grade on the devices and its recommended applications. 1.5 pin configuration (top view) 1.5.1 v850e/sj3-h 144-pin plastic lqfp (fine pitch) (20 20) pd70f3474gja-gae-g pd70f3476gja-gae-g pd70f3478gja-gae-g pd70f3475gja-gae-g pd70f3477gja-gae-g pd70f3479gja-gae-g pd70f3931gja-gae-g pd70f3932gja-gae-g pd70f3933gja-gae-g pd70f3934gja-gae-g pd70f3935gja-gae-g pd70f3936gja-gae-g pd70f3937gja-gae-g pd70f3938gja-gae-g pd70f3939gja-gae-g chapter 1 introduction user?s manual u19201ej3v0ud 30 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0 pcd3/txdb1 pcd2/rxdb1 pcd1/txdb0 pcd0/rxdb0 p915/a15 note 7 /intp6/tip50/top50 p914/a14 note 7 /intp5/tip51/top51 p913/a13 note 7 /intp4 p912/a12 note 7 /sckb3 av ref0 av ss p10/ano0 p11/ano1 av ref1 p00/tip61/top61/sda04 note 1 p01/tip60/top60/scl04 note 1 flmd0 note 2 v dd regc note 3 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst note 4 p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0/intp2 p30/txda0/sob4 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01/ctxd1 note 5 p34/tip10/top10/crxd1 note 5 p35/tip11/top11 p36/ctxd0 note 6 /ietx0 p37/crxd0 note 6 /ierx0 ev ss ev dd p38/txda2/sda00/sib2 p39/rxda2/scl00/sckb2 p50/kr0/tiq01/toq01/rtp00 p51/intp7/kr1/tiq02/toq02/rtp01 p52/kr2/tiq03/toq03/rtp02/ddi p53/sib2/kr3/tiq00/toq00/rtp03/ddo p54/sob2/kr4/rtp04/dck p55/sckb2/kr5/rtp05/dms p60/rtp10/rxda4/sie0 note 1 p61/rtp11/txda4/soe0 note 1 p62/rtp12/scke0 note 1 p63/rtp13/sie1 note 1 /kr4 p64/rtp14/soe1 note 1 /kr5 p65/rtp15/scke1 note 1 /kr2/tiq03/toq03 p66/sib5/intp9/kr3/tiq00/toq00 p67/sob5/rxda5/sda05 note 1 p68/sckb5/txda5/scl05 note 1 p69/tip70/top70/tenc70 p610/tip71/tenc71 p611/top71/tecr7 p612/tip80/top80/tenc80 p613/tip81/top81/tenc81 p614/sda03/tecr8 p615/scl03 p80/rxda3/intp8/rc1ck1hz p81/txda3/rc1cko/rc1ckdiv p90/a0 note 7 /kr6/txda1/sda02 p91/a1 note 7 /kr7/rxda1/kr7/scl02 p92/a2 note 7 /tip41/top41 p93/a3 note 7 /tip40/top40/intp8 p94/a4 note 7 /tip31/top31 p95/a5 note 7 /tip30/top30/intp5 p96/a6 note 7 /tip21/top21 p97/a7 note 7 /sib1/tip20/top20 p98/a8 note 7 /sob1 p99/a9 note 7 /sckb1 p910/a10 note 7 /sib3 p911/a11 note 7 /sob3 p70/ani0 note 8 p71/ani1 note 8 p72/ani2 note 8 p73/ani3 note 8 p74/ani4 note 8 p75/ani5 note 8 p76/ani6 note 8 p77/ani7 note 8 p78/ani8 note 8 p79/ani9 note 8 p710/ani10 note 8 p711/ani11 note 8 p712/ani12 note 8 p713/ani13 note 8 p714/ani14 note 8 p715/ani15 note 8 pdh7/a23 pdh6/a22 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 notes 1. sie0, soe0, scke0, sie1, soe1, scke1, scl04, sda04, scl05, and sda05 are available only in products other than the pd70f3931 (v850e/sj3-h), 70f393 2 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). 2. set this pin to low level in the normal operation mode. 3. connect the regc pin to v ss via a 4.7 f capacitor. 4. fix this pin to the low level from when the reset status has been released until the ocdm.ocdm0 bit is cleared (0) when the on-chip debug func tion is not used. for details, see 4.6.3 cautions on on-chip debug pins . in addition, this pin incorporates a pull-down re sistor and it can be disc onnected by clearing the ocdm.ocdm0 bit. 5. ctxd1 and crxd1 are valid only in t he can controller (2-channel) version. 6. ctxd0 and crxd0 are valid only in the can controller version. 7. port 9 cannot be used as port pins or other alter nate-function pins when the a0 to a15 pins are used in the separate bus mode. 8. to use port 7 (p70/ani0 to p715/ani15) as a/d conv erter function pins and port i/o pins in mix, be sure to observe usage cautions (see 13.6 (4) alternate i/o ). chapter 1 introduction user?s manual u19201ej3v0ud 31 pin names a0 to a23: ad0 to ad15: adtrg: ani0 to ani15: ano0, ano1: ascka0: astb: av ref0 , av ref1 : av ss : bv dd : bv ss : clkout: crxd0, crxd1: cs1 to cs3: ctxd0, ctxd1: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: ierx0: ietx0: intp0 to intp9: kr0 to kr7: nmi: p00 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p60 to p615: p70 to p715: p80, p81: p90 to p915: pcd0 to pcd3: pcm0 to pcm5: pcs0 to pcs7: pct0 to pct7: pdh0 to pdh7: pdl0 to pdl15: rc1ck1hz, rc1ckdiv, rc1cko: address bus address/data bus a/d trigger input analog input analog output asynchronous serial clock address strobe analog reference voltage analog v ss power supply for bus interface ground for bus interface clock output can receive data chip select can transmit data debug clock debug data input debug data output debug mode select debug reset power supply for port ground for port flash programming mode hold acknowledge hold request iebus receive data iebus transmit data external interrupt input key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port cd port cm port cs port ct port dh port dl real-time counter clock output rd: regc: reset: rtp00 to rtp05, rtp10 to rtp15: rxda0 to rxda5, rxdb0, rxdb1: sckb0 to sckb5, scke0, scke1: scl00 to scl05: sda00 to sda05: sib0 to sib5, sie0, sie1: sob0 to sob5, soe0, soe1: tecr7, tecr8: tenc70, tenc71, tenc80, tenc81: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tip60, tip61, tip70, tip71, tip80, tip81, tiq00 to tiq03: top00, top01, top10, top11, top20, top21, top30, top31, top40, top41, top50, top51, top60, top61, top70, top71, top80, top81, toq00 to toq03: txda0 to txda5, txdb0, txdb1: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer encoder clear input timer encoder input timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction user?s manual u19201ej3v0ud 32 1.5.2 v850e/sk3-h 176-pin plastic lqfp (fine pitch) (24 24) pd70f3480gma-gar-g pd70f3481gma-gar-g pd70f3482gma-gar-g pd70f3486gma-gar-g pd70f3487gma-gar-g pd70f3488gma-gar-g pd70f3925gma-gar-g pd70f3926gma-gar-g pd70f3927gma-gar-g chapter 1 introduction user?s manual u19201ej3v0ud 33 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 p133 p132 p131 p130 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0 pcd3/txdb1 pcd2/rxdb1 pcd1/txdb0 pcd0/rxdb0 p153/intp6 p152/intp9 p151/txda1 p150/rxda1/kr7 p915/a15 note 6 /intp6/tip50/top50 p914/a14 note 6 /intp5/tip51/top51 p913/a13 note 6 /intp4 p912/a12 note 6 /sckb3 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 p70/ani0 note 7 p71/ani1 note 7 p72/ani2 note 7 p73/ani3 note 7 p74/ani4 note 7 p75/ani5 note 7 p76/ani6 note 7 p77/ani7 note 7 p78/ani8 note 7 p79/ani9 note 7 p710/ani10 note 7 p711/ani11 note 7 p712/ani12 note 7 p713/ani13 note 7 p714/ani14 note 7 p715/ani15 note 7 p145 p144 p143 p142 p141 p140 bv ss bv dd pdh7/a23 pdh6/a22 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 p50/kr0/tiq01/toq01/rtp00 p51/intp7/kr1/tiq02/toq02/rtp01 p52/kr2/tiq03/toq03/rtp02/ddi p53/sib2/kr3/tiq00/toq00/rtp03/ddo p54/sob2/kr4/rtp04/dck p55/sckb2/kr5/rtp05/dms p56/rxda4 p57/txda4 p60/rtp10/rxda4/sie0 p61/rtp11/txda4/soe0 p62/rtp12/scke0 p63/rtp13/sie1/kr4 p64/rtp14/soe1/kr5 p65/rtp15/scke1/kr2/tiq03/toq03 p66/sib5/intp9/kr3/tiq00/toq00 p67/sob5/rxda5/sda05 p68/sckb5/txda5/scl05 p69/tip70/top70/tenc70 p610/tip71/tenc71 p611/top71/tecr7 p612/tip80/top80/tenc80 p613/tip81/top81/tenc81 p614/sda03/tecr8 p615/scl03 ev dd ev ss p80/rxda3/intp8/rc1ck1hz p81/txda3/rc1cko/rc1ckdiv p82/sda05 p83/scl05 p84/rxda5 p85/txda5 p90/a0 note 6 /kr6/txda1/sda02 p91/a1 note 6 /kr7/rxda1/kr7/scl02 p92/a2 note 6 /tip41/top41 p93/a3 note 6 /tip40/top40/intp8 p94/a4 note 6 /tip31 /top31 p95/a5 note 6 /tip30/top30/intp5 p96/a6 note 6 / tip21/top21 p97/a7 note 6 /sib1/tip20/top20 p98/a8 note 6 /sob1 p99/a9 note 6 /sckb1 p910/a10 note 6 /sib3 p911/a11 note 6 /sob3 av ref0 av ss p10/ano0 p11/ano1 av ref1 p00/tip61/top61/sda04 p01/tip60/top60/scl04 p20/sda04 p21/scl04 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst note 3 p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0/intp2 p43 p44/ietx0 p45/ierx0 p30/txda0/sob4 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01/ctxd1 note 4 p34/tip10/top10/crxd1 note 4 p35/tip11/top11 p36/ctxd0 note 5 /ietx0 p37/crxd0 note 5 /ierx0 ev ss ev dd p38/txda2/sda00/sib2 p39/rxda2/scl00/sckb2 p310/sob2 p311/txda2 p312/rxda2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 notes 1. set this pin to low level in the normal operation mode. 2. connect the regc pin to v ss via a 4.7 f capacitor. 3. fix this pin to the low level from when the reset status has been released until the ocdm.ocdm0 bit is cleared (0) when the on-chip debug func tion is not used. for details, see 4.6.3 cautions on on-chip debug pins . in addition, this pin incorporates a pull-down resistor and it can be disconnected by clearing the ocdm.ocdm0 bit. 4. ctxd1 and crxd1 are valid only in t he can controller (2-channel) version. 5. ctxd0 and crxd0 are valid only in the can controller version. 6. port 9 cannot be used as port pins or other alternat e-function pins when the a0 to a15 pins are used in the separate bus mode. 7. to use port 7 (p70/ani0 to p715/ani15) as a/d converter function pins and port i/o pins in mix, be sure to observe usage cautions (see 13.6 (4) alternate i/o ). chapter 1 introduction user?s manual u19201ej3v0ud 34 pin names a0 to a23: ad0 to ad15: adtrg: ani0 to ani15: ano0, ano1: ascka0: astb: av ref0 , av ref1 : av ss : bv dd : bv ss : clkout: crxd0, crxd1: cs1 to cs3: ctxd0, ctxd1: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: ierx0: ietx0: intp0 to intp9: kr0 to kr7: nmi: p00 to p06: p10, p11: p20, p21: p30 to p312: p40 to p45: p50 to p57: p60 to p615: p70 to p715: p80 to p85: p90 to p915: p130 to p133: p140 to p145: p150 to p153: pcd0 to pcd3: pcm0 to pcm5: pcs0 to pcs7: pct0 to pct7: pdh0 to pdh7: address bus address/data bus a/d trigger input analog input analog output asynchronous serial clock address strobe analog reference voltage analog v ss power supply for bus interface ground for bus interface clock output can receive data chip select can transmit data debug clock debug data input debug data output debug mode select debug reset power supply for port ground for port flash programming mode hold acknowledge hold request iebus receive data iebus transmit data external interrupt input key return non-maskable interrupt request port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port 13 port 14 port 15 port cd port cm port cs port ct port dh pdl0 to pdl15: rc1ck1hz, rc1ckdiv, rc1cko: rd: regc: reset: rtp00 to rtp05, rtp10 to rtp15: rxda0 to rxda5, rxdb0, rxdb1: sckb0 to sckb5, scke0, scke1: scl00 to scl05: sda00 to sda05: sib0 to sib5, sie0, sie1: sob0 to sob5, soe0, soe1: tecr7, tecr8: tenc70, tenc71, tenc80, tenc81: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tip60, tip61, tip70, tip71, tip80, tip81, tiq00 to tiq03: top00, top01, top10, top11, top20, top21, top30, top31, top40, top41, top50, top51, top60, top61, top70, top71, top80, top81, toq00 to toq03: txda0 to txda5, txdb0, txdb1: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port dl real-time counter clock output read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer encoder clear input timer encoder input timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction user?s manual u19201ej3v0ud 35 1.6 function block configuration 1.6.1 internal block diagram (1) v850e/sj3-h toq00 to toq03 tiq00 to tiq03 rtp00 to rtp05, rtp10 to rtp15 nmi intp0 to intp9 top00 to top80, top01 to top81 tip00 to tip80, tip01 to tip81, tecr7, tecr8, tenc70, tenc71, tenc80, tenc81 kr0 to kr7 rto dmac intc rom correction note 1 note 2 ram rom pdl0 to pdl15 pdh0 to pdh7 pct0 to pct7 pcs0 to pcs7 pcm0 to pcm5 pcd0 to pcd3 p90 to p915 p80, p81 p70 to p715 p60 to p615 p50 to p55 p40 to p42 p30 to p39 p10, p11 p00 to p06 av ref1 ano0, ano1 ani0 to ani15 av ss av ref0 adtrg v850e1 cpu cpu memc bcu pc alu hldrq hldak astb rd wait wr0, wr1 a0 to a23 ad0 to ad15 cs1 to cs3 rc1ck1hz, rc1ckdiv, rc1cko rtc can1 note 6 ctxd1 note 6 crxd1 note 6 iebus can0 note 5 ctxd0 note 5 /ietx0 crxd0 note 5 /ierx0 flmd0 flmd1 cg pll sscg lvi clm clkout xt1 xt2 x1 x2 reset v dd v ss regc bv dd bv ss ev dd ev ss drst dms ddi dck ddo sib0/sda01 sob0/scl01 sckb0 csib0 i 2 c01 sie1 note 3 soe1 note 3 scke1 note 3 csie1 note 3 sib1 to sib3 sob1 to sob3 sckb1 to sckb3 csib1 to csib3 txda2/sda00 rxda2/scl00 uarta2 i 2 c00 txda4/soe0 note 3 rxda4/sie0 note 3 scke0 note 3 uarta4 note 3 csie0 txda0/sob4 rxda0/sib4 ascka0/sckb4 uarta0 csib4 txda3 rxda3 uarta3 txda1/sda02 rxda1/scl02 uarta1 i 2 c02 txda5/sckb5/scl05 note 3 rxda5/sob5/sda05 note 3 sib5 csib5 uarta5 note 3 i 2 c05 txdb0, txdb1 rxdb0, rxdb1 uartb0, uartb1 sda03, sda04 note 3 scl03, scl04 note 3 i 2 c03, i 2 c04 note 3 16-bit timer/ counter q: 1 ch 32-bit barrel shifter instruction queue multiplier 32 32 64 general-purpose registers 32 bits 32 system registers a/d converter d/a converter key return function watchdog timer 2 watch timer 16-bit timer/ counter p: 9 ch 16-bit interval timer m: 3 ch internal oscillator regulator ports dcu serial interfaces note 7 note 4 expanded internal ram note 3 notes 1. 512/768/1024/1280/1536 kb (flash memory) (see table 1-1 ) 2. 60 kb (see table 1-1 ) 3. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h) 4. 16/32 kb (see table 1-1 ) 5. can controller version only 6. can controller (2-channel) version only chapter 1 introduction user?s manual u19201ej3v0ud 36 notes 7. another type of the block diagram is available in accordance with the combination of port sharing. sib0/sda01 sob0/scl01 sckb0 csib0 i 2 c01 sie1 note 3 soe1 note 3 scke1 note 3 csie1 note 3 sib1, sib3 sob1, sob3 sckb1, sckb3 csib1, csib3 txda2/sib2/sda00 rxda2/sckb2/scl00 csib2 uarta2 i 2 c00 txda4/soe0 note 3 rxda4/sie0 note 3 scke0 note 3 uarta4 csie0 txda0/sob4 rxda0/sib4 ascka0/sckb4 uarta0 csib4 txda3 rxda3 uarta3 txda1/sda02 rxda1/scl02 uarta1 i 2 c02 txda5/sckb5/scl05 note 3 rxda5/sob5/sda05 note 3 sib5 csib5 uarta5 i 2 c05 txdb0, txdb1 rxdb0, rxdb1 uartb0, uartb1 sda03, sda04 note 3 scl03, scl04 note 3 i 2 c03, i 2 c04 note 3 note 8 note 3 note 3 8. the serial transmit data output pin (sob2) is not provided. chapter 1 introduction user?s manual u19201ej3v0ud 37 (2) v850e/sk3-h toq00 to toq03 tiq00 to tiq03 rtp00 to rtp05, rtp10 to rtp15 nmi intp0 to intp9 16-bit timer/ counter q: 1 ch top00 to top80, top01 to top81 tip00 to tip80, tip01 to tip81, tecr7, tecr8, tenc70 to tenc71, tenc80 to tenc81 kr0 to kr7 rto dmac intc ram rom pdl0 to pdl15 pdh0 to pdh7 pct0 to pct7 pcs0 to pcs7 pcm0 to pcm5 pcd0 to pcd3 p150 to p153 p140 to p145 p130 to p133 p90 to p915 p80 to p85 p70 to p715 p60 to p615 p50 to p57 p40 to p45 p30 to p312 p20, p21 p10, p11 p00 to p06 av ref1 ano0, ano1 ani0 to ani15 av ss av ref0 adtrg v850e1 cpu cpu memc bcu pc alu hldrq hldak astb rd wait wr0, wr1 a0 to a23 ad0 to ad15 cs1 to cs3 rc1ck1hz, rc1ckdiv, rc1cko rtc can1 note 5 ctxd1 note 5 crxd1 note 5 ctxd0 note 4 crxd0 note 4 iebus ietx0 ierx0 flmd0 flmd1 cg pll sscg lvi clm clkout xt1 xt2 x1 x2 reset v dd v ss regc bv dd bv ss ev dd ev ss drst dms ddi dck ddo sib0/sda01 sob0/scl01 sckb0 csib0 i 2 c01 sie1 soe1 scke1 csie1 sib1 to sib3 sob1 to sob3 sckb1 to sckb3 csib1 to csib3 txda2/sda00 rxda2/scl00 uarta2 i 2 c00 txda4/soe0 rxda4/sie0 scke0 uarta4 csie0 txda0/sob4 rxda0/sib4 ascka0/sckb4 uarta0 csib4 txda3 rxda3 uarta3 txda1/sda02 rxda1/scl02 uarta1 i 2 c02 txda5/sckb5/scl05 rxda5/sob5/sda05 sib5 csib5 uarta5 i 2 c05 txdb0, txdb1 rxdb0, rxdb1 uartb0, uartb1 sda03, sda04 scl03, scl04 i 2 c03, i 2 c04 16-bit timer/ counter p: 9 ch 16-bit interval timer m: 3 ch note 1 note 2 32-bit barrel shifter instruction queue multiplier 32 32 64 general-purpose registers 32 bits 32 system registers internal oscillator ports a/d converter d/a converter key return function watchdog timer 2 watch timer regulator dcu serial interfaces note 6 rom correction can0 note 4 note 3 expanded internal ram notes 1. 1024/1280/1536 kb (flash memory) (see table 1-1 ) 2. 60 kb (see table 1-1 ) 3. 16/32 kb (see table 1-1 ) 4. can controller version only 5. can controller (2-channel) version only chapter 1 introduction user?s manual u19201ej3v0ud 38 note 6. an example of port sharing combinations is shown in the following block diagram. sib2/sda00 sob2/scl00 sckb2 csib2 i 2 c00 sib0/sda01 sob0/scl01 sckb0 csib0 i 2 c01 sie0, sie1 soe0, soe1 scke0, scke1 csie0, csie1 sib1, sib3, sib5 sob1, sob3, sob5 sckb1, sckb3, sckb5 csib1, csib3, csib5 txda0/sob4 rxda0/sib4 ascka0/sckb4 uarta0 csib4 txda1 to txda5 rxda1 to rxda5 uarta1 to uarta5 txdb0, txdb1 rxdb0, rxdb1 uartb0, uartb1 sda02 to sda04 scl02 to scl04 i 2 c02 to i 2 c05 chapter 1 introduction user?s manual u19201ej3v0ud 39 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single -clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (32 bits 32 bits 64 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space a nd the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the pref etched instruction code is stored in a cpu internal instruction queue. the bcu controls a memory controller (memc) and accesses an external memory and an expanded internal ram. (a) memory controller (memc) controls access to sram, ex ternal rom, and external i/o. (3) rom this is a 1536/1280/1024/768/512 kb flash memory mapped to addresses 0000 000h to 017ffffh/0000000h to 013ffffh/0000000h to 00fffffh/0000000h to 00bffffh/0000000h to 007ffffh. it can be accessed from the cpu in one clock during instruction fetch. (4) ram this is a 60 kb ram mapped to addresses 3ff0000h to 3ffefffh. it can be accessed from the cpu in one clock during data access. (5) expanded internal ram this is a 32/16 kb ram mapped to addresses 3f e4000h to 3febfffh/3fe8000h to 3febfffh. the expanded internal ram can be accessed in 3 bus cycles (min.). (6) interrupt controller (intc) this controller handles hardware interrupt requests (nm i, intp0 to intp9) from on-chip peripheral hardware and external hardware. eight levels of interrupt priori ties can be specified for these interrupt requests, and multiple servicing control can be performed. (7) clock generator (cg) a main clock oscillator that generates the main clock oscillation frequency (f x ) and a subclock oscillator that generates the subclock oscillation frequency (f xt ) are available. as the main clock frequency, pll input clock frequency (f plli ) is used as it is in the clock-through mode, is mu ltiplied by eight or divided by 2 after multiplied by eight in the pll mode, and is multiplied by eight or twelve in the sscg mode. the cpu clock frequency (f cpu ) can be selected from seven types: f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . as the peripheral clock frequency (f xp ), the main clock frequency (f xx ) is used in the pll mode, and the f plli multiplied by eight or divided by 2 after multipli ed by eight with pll is used in the sscg mode. chapter 1 introduction user?s manual u19201ej3v0ud 40 (8) internal oscillator an internal oscillator is provided on chip. the oscillation frequency is 220 khz (typ.). an internal oscillator supplies the clock for watchdog timer 2 and timer m. (9) timer/counter nine-channel 16-bit timer/event counter p (tmp) (encoder count function is provided for tmp7 and tmp8), one-channel 16-bit timer/event counter q (tmq), and thre e-channel 16-bit interval timer m (tmm) are provided on chip. (10) watch timer this timer counts the reference time period (0.5 s or 0.25 s) for counting the cloc k (the 32.768 khz from the subclock or the 32.768 khz f brg from prescaler 3). the watch timer can also be used as an interval timer for the main clock. (11) real-time counter (for watch) the real-time counter counts t he reference time (1 second) from the s ubclock (32.768 khz) or main clock for watch counting. this can also be used as the interval timer based on the main clock at the same time. dedicated hardware counters for year, month, week, day, hour, minute, and second are provided, and the real- time counter can count up to 99 years. (12) watchdog timer 2 a watchdog timer is provided on chip to detect inadv ertent program loops, system abnormalities, etc. either the internal oscillation clock, the main clock, or the subclock can be selected as the source clock. watchdog timer 2 generates a non-maskable interrupt request signal (intwdt2) or a system reset signal (wdt2res) after an overflow occurs. with the option byte function, the operation mode of watchdog timer 2 can be fixed to the reset mode. (13) serial interface the v850e/sj3-h and v850e/sk3-h include five kinds of serial interfaces: asynchronous serial interface a (uarta), asynchronous serial interface b (uartb), 3-wire variable-length serial interface b (csib), 3-wire variable-length serial interface e (csie), and an i 2 c bus interface (i 2 c). in the case of uarta, data is transferred via the txda0 to txda5 pins and rxda0 to rxda5 pins. in the case of uartb, data is transferred via t he txdb0 and txdb1 pins and rxdb0 and rxdb1 pins. in the case of csib, data is transferred via the sob0 to sob5 pins, sib0 to sib5 pins, and sckb0 to sckb5 pins. in the case of csie, data is transferred via the soe0 note , soe1 note , sie0 note , sie1 note , scke0 note , and scke1 note pins. in the case of i 2 c, data is transferred via the sda00 to sda03, sda04 note , sda05 note , scl00 to scl03, scl04 note , and scl05 note pins. note not available in the pd70f3931 (v850e/sj3-h), and 70f3932 (v850e/sj3-h), 70f3933 (v850e/sj3- h). (14) iebus controller the iebus controller is a small-scale digital data transmission system for transferring data between units. (15) can controller the can controller is a small-scale digital data transmission system for transferring data between units. the can controller is provided only in the can controller version (see table 1-1 ). chapter 1 introduction user?s manual u19201ej3v0ud 41 (16) a/d converter this 10-bit a/d converter includes 16 analog input pins. conversion is performed using the successive approximation method. (17) d/a converter a two-channel, 8-bit-resolution d/a converter that uses the r-2r ladder method is provided on chip. (18) dma controller a 4-channel dma controller is provided on chip. this controller transfers data between the internal ram, on- chip peripheral i/o, external memories, and expanded inte rnal ram in response to interrupt requests sent by on-chip peripheral i/o. (19) rom correction a rom correction function that replaces part of a progra m in the internal rom with a program in the internal ram is provided. up to eight correction addresses can be specified. (20) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to key input pins (8 channels). (21) real-time output function the real-time output function transfe rs preset 6-bit data to output latches upon the occurrence of a timer compare register match signal. (22) crc function a crc operation circuit that generates 16-bit crc (cyclic redundancy check) code upon setting of 8-bit data is provided on chip. (23) dcu (debug control unit) an on-chip debug function via an on-chip debug emulat or that uses the jtag (joint test action group) communication specifications is pr ovided. switching between the normal port function and on-chip debugging function is done with the control pin input level and the on-chip debug mode register (ocdm). chapter 1 introduction user?s manual u19201ej3v0ud 42 (24) ports the general-purpose port functions and cont rol pin functions are listed below. port i/o alternate function p0 7-bit i/o timer i/o, serial interface note 2 , nmi, external interrupt, a/d converter trigger, debug reset p1 2-bit i/o d/a converter analog output p2 note 1 2-bit i/o (v850e/sk3-h) serial interface p3 10-bit i/o (v850e/sj3-h) 13-bit i/o (v850e/sk3-h) external interrupt, serial interface, timer i/o, can data i/o note 3 , iebus data i/o p4 3-bit i/o (v850e/sj3-h) 6-bit i/o (v850e/sk3-h) serial interface, external interrupt, iebus data i/o note 1 p5 6-bit i/o (v850e/sj3-h) 8-bit i/o (v850e/sk3-h) timer i/o, real-time output, key interrupt input, external interrupt, serial interface, debug i/o p6 16-bit i/o real-time output, serial interface, timer i/o, encoder input, key interrupt input, external interrupt p7 16-bit i/o a/d converter analog input p8 2-bit i/o (v850e/sj3-h) 6-bit i/o (v850e/sk3-h) serial interface, external interrupt, real-time counter output p9 16-bit i/o external address bus, serial interface, key interrupt input, timer i/o, external interrupt p13 note 1 4-bit i/o (v850e/sk3-h) ? p14 note 1 6-bit i/o (v850e/sk3-h) ? p15 note 1 4-bit i/o (v850e/sk3-h) serial interface, external interrupt, key interrupt input pcd 4-bit i/o serial interface pcm 6-bit i/o external control signal pcs 8-bit i/o chip select output pct 8-bit i/o external control signal pdh 8-bit i/o external address bus pdl 16-bit i/o external address/data bus, fl ash memory programming mode input signal notes 1. v850e/sk3-h only 2. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) 3. can controller version only user?s manual u19201ej3v0ud 43 chapter 2 pin functions 2.1 list of pin functions the names and functions of the pins of the v 850e/sj3-h and v850e/sk3-h are described below. there are four types of pin i/o buffer power supplies: av ref0 , av ref1 , bv dd , and ev dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies (a) v850e/sj3-h power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports cd, cm, cs, ct, dh, dl ev dd reset, ports 0, 3 to 6, 8, 9 (b) v850e/sk3-h power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports 13, 14, cd, cm, cs, ct, dh, dl ev dd reset, ports 0, 2 to 6, 8, 9, 15 chapter 2 pin functions user?s manual u19201ej3v0ud 44 (1) port pins (1/6) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function p00 6 6 tip61/top61/sda04 note 3 p01 7 7 tip60/top60/scl04 note 3 p02 17 19 nmi p03 18 20 intp0/adtrg p04 19 21 intp1 p05 note 1 20 22 intp2/drst p06 21 23 i/o port 0 7-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. intp3 p10 3 3 ano0 p11 4 4 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. ano1 p20 note 2 ? 8 sda04 note 2 p21 note 2 ? 9 i/o port 2 (v850e/sk3-h only) 2-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. scl04 note 2 p30 25 30 txda0/sob4 p31 26 31 rxda0/intp7/sib4 p32 27 32 ascka0/sckb4/tip00/top00 p33 28 33 tip01/top01/ctxd1 note 4 p34 29 34 tip10/top10/crxd1 note 4 p35 30 35 tip11/top11 p36 31 36 ctxd0 note 5 /ietx0 p37 32 37 crxd0 note 5 /ierx0 p38 35 40 txda2/sda00/sib2 p39 36 41 rxda2/scl00/sckb2 p310 note 2 ? 42 sob2 note 2 p311 note 2 ? 43 txda2 note 2 p312 note 2 ? 44 i/o port 3 v850e/sj3-h: 10-bit i/o port v850e/sk3-h: 13-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. rxda2 note 2 notes 1. fix this pin to the low level from when the reset status has been released unt il the ocdm.ocdm0 bit is cleared (0) when the on-chip debug functi on is not used. for details, see 4.6.3 cautions on on-chip debug pins . in addition, this pin incorporates a pull-do wn resistor and it can be disconnected by clearing the ocdm.ocdm0 bit. 2. v850e/sk3-h only 3. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) 4. can controller (2-channel) version only 5. can controller version only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 45 (2/6) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function p40 22 24 sib0/sda01 p41 23 25 sob0/scl01 p42 24 26 sckb0/intp2 p43 note 1 ? 27 ? p44 note 1 ? 28 ietx0 note 1 p45 note 1 ? 29 i/o port 4 v850e/sj3-h: 3-bit i/o port v850e/sk3-h: 6-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. ierx0 note 1 p50 37 45 kr0/tiq01/toq01/rtp00 p51 38 46 intp7/kr1/tiq02/toq02/rtp01 p52 39 47 kr2/tiq03/toq03/rtp02/ddi p53 40 48 sib2/kr3/tiq00/toq00/rtp03/ddo p54 41 49 sob2/kr4/rtp04/dck p55 42 50 sckb2/kr5/rtp05/dms p56 note 1 ? 51 rxda4 note 1 p57 note 1 ? 52 i/o port 5 v850e/sj3-h: 6-bit i/o port v850e/sk3-h: 8-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. txda4 note 1 p60 43 53 rtp10/rxda4/sie0 note 2 p61 44 54 rtp11/txda4/soe0 note 2 p62 45 55 rtp12/scke0 note 2 p63 46 56 rtp13/sie1 note 2 /kr4 p64 47 57 rtp14/soe1 note 2 /kr5 p65 48 58 rtp15/scke1 note 2 /kr2/tiq03/toq03 p66 49 59 sib5/intp9/kr3/tiq00/toq00 p67 50 60 sob5/rxda5/sda05 note 2 p68 51 61 sckb5/txda5/scl05 note 2 p69 52 62 tip70/top70/tenc70 p610 53 63 tip71/tenc71 p611 54 64 top71/tecr7 p612 55 65 tip80/top80/tenc80 p613 56 66 tip81/top81/tenc81 p614 57 67 sda03/tecr8 p615 58 68 i/o port 6 16-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. scl03 notes 1. v850e/sk3-h only 2. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 46 (3/6) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function p70 144 176 ani0 p71 143 175 ani1 p72 142 174 ani2 p73 141 173 ani3 p74 140 172 ani4 p75 139 171 ani5 p76 138 170 ani6 p77 137 169 ani7 p78 136 168 ani8 p79 135 167 ani9 p710 134 166 ani10 p711 133 165 ani11 p712 132 164 ani12 p713 131 163 ani13 p714 130 162 ani14 p715 129 161 i/o port 7 16-bit i/o port input/output can be specified in 1-bit units. ani15 p80 59 71 rxda3/intp8/rc1ck1hz p81 60 72 txda3/rc1cko/rc1ckdiv p82 note ? 73 sda05 note p83 note ? 74 scl05 note p84 note ? 75 rxda5 note p85 note ? 76 i/o port 8 v850e/sj3-h: 2-bit i/o port v850e/sk3-h: 6-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. txda5 note note v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 47 (4/6) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function p90 61 77 a0/kr6/txda1/sda02 p91 62 78 a1/kr7/rxda1/kr7/scl02 p92 63 79 a2/tip41/top41 p93 64 80 a3/tip40/top40/intp8 p94 65 81 a4/tip31/top31 p95 66 82 a5/tip30/top30/intp5 p96 67 83 a6/tip21/top21 p97 68 84 a7/sib1/tip20/top20 p98 69 85 a8/sob1 p99 70 86 a9/sckb1 p910 71 87 a10/sib3 p911 72 88 a11/sob3 p912 73 89 a12/sckb3 p913 74 90 a13/intp4 p914 75 91 a14/intp5/tip51/top51 p915 76 92 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. a15/intp6/tip50/top50 p130 note ? 125 ? p131 note ? 126 ? p132 note ? 127 ? p133 note ? 128 i/o port 13 (v850e/sk3-h only) 4-bit i/o port input/output can be specified in 1-bit units. ? p140 note ? 155 ? p141 note ? 156 ? p142 note ? 157 ? p143 note ? 158 ? p144 note ? 159 ? p145 note ? 160 i/o port 14 (v850e/sk3-h only) 6-bit i/o port input/output can be specified in 1-bit units. ? p150 note ? 93 rxda1 note /kr7 note p151 note ? 94 txda1 note p152 note ? 95 intp9 note p153 note ? 96 i/o port 15 (v850e/sk3-h only) 4-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. intp6 note note v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 48 (5/6) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function pcd0 77 97 rxdb0 pcd1 78 98 txdb0 pcd2 79 99 rxdb1 pcd3 80 100 i/o port cd 4-bit i/o port input/output can be specified in 1-bit units. txdb1 pcm0 85 105 wait pcm1 86 106 clkout pcm2 87 107 hldak pcm3 88 108 hldrq pcm4 89 109 ? pcm5 90 110 i/o port cm 6-bit i/o port input/output can be specified in 1-bit units. ? pcs0 81 101 ? pcs1 82 102 cs1 pcs2 83 103 cs2 pcs3 84 104 cs3 pcs4 91 111 ? pcs5 92 112 ? pcs6 93 113 ? pcs7 94 114 i/o port cs 8-bit i/o port input/output can be specified in 1-bit units. ? pct0 95 115 wr0 pct1 96 116 wr1 pct2 97 117 ? pct3 98 118 ? pct4 99 119 rd pct5 100 120 ? pct6 101 121 astb pct7 102 122 i/o port ct 8-bit i/o port input/output can be specified in 1-bit units. ? pdh0 121 145 a16 pdh1 122 146 a17 pdh2 123 147 a18 pdh3 124 148 a19 pdh4 125 149 a20 pdh5 126 150 a21 pdh6 127 151 a22 pdh7 128 152 i/o port dh 8-bit i/o port input/output can be specified in 1-bit units. a23 remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 49 (6/6) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function pdl0 105 129 ad0 pdl1 106 130 ad1 pdl2 107 131 ad2 pdl3 108 132 ad3 pdl4 109 133 ad4 pdl5 110 134 ad5/flmd1 pdl6 111 135 ad6 pdl7 112 136 ad7 pdl8 113 137 ad8 pdl9 114 138 ad9 pdl10 115 139 ad10 pdl11 116 140 ad11 pdl12 117 141 ad12 pdl13 118 142 ad13 pdl14 119 143 ad14 pdl15 120 144 i/o port dh 16-bit i/o port input/output can be specified in 1-bit units. ad15 remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 50 (2) non-port pins (1/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function a0 61 77 p90/kr6/txda1/sda02 a1 62 78 p91/kr7/rxda1/kr7/scl02 a2 63 79 p92/tip41/top41 a3 64 80 p93/tip40/top40/intp8 a4 65 81 p94/tip31 /top31 a5 66 82 p95/tip30/top30/intp5 a6 67 83 p96/tip21/top21 a7 68 84 p97/sib1/tip20/top20 a8 69 85 p98/sob1 a9 70 86 p99/sckb1 a10 71 87 p910/sib3 a11 72 88 p911/sob3 a12 73 89 p912/sckb3 a13 74 90 p913/intp4 a14 75 91 p914/intp5/tip51/top51 a15 76 92 output address bus for external memory (when using separate bus) port 9 cannot be used as port pins or other alternate- function pins when the a0 to a15 pins are used in the separate bus mode. n-ch open-drain output selectable 5 v tolerant. p915/intp6/tip50/top50 a16 121 145 pdh0 a17 122 146 pdh1 a18 123 147 pdh2 a19 124 148 pdh3 a20 125 149 pdh4 a21 126 150 pdh5 a22 127 151 pdh6 a23 128 152 output address bus for external memory pdh7 remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 51 (2/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function ad0 105 129 pdl0 ad1 106 130 pdl1 ad2 107 131 pdl2 ad3 108 132 pdl3 ad4 109 133 pdl4 ad5 110 134 pdl5/flmd1 ad6 111 135 pdl6 ad7 112 136 pdl7 ad8 113 137 pdl8 ad9 114 138 pdl9 ad10 115 139 pdl10 ad11 116 140 pdl11 ad12 117 141 pdl12 ad13 118 142 pdl13 ad14 119 143 pdl14 ad15 120 144 i/o address/data bus for external memory pdl15 adtrg 18 20 input a/d converter external trigger input, 5 v tolerant p03/intp0 ani0 144 176 p70 ani1 143 175 p71 ani2 142 174 p72 ani3 141 173 p73 ani4 140 172 p74 ani5 139 171 p75 ani6 138 170 p76 ani7 137 169 p77 ani8 136 168 p78 ani9 135 167 p79 ani10 134 166 p710 ani11 133 165 p711 ani12 132 164 p712 ani13 131 163 p713 ani14 130 162 p714 ani15 129 161 input analog voltage input for a/d converter p715 ano0 3 3 p10 ano1 4 4 output analog voltage output for d/a converter p11 ascka0 27 32 input uarta0 baud rate clock input, 5 v tolerant p32/sckb4/tip00/top00 astb 101 121 output address strobe signal output for external memory pct6 remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 52 (3/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function av ref0 1 1 reference voltage input for a/d converter, positive power supply for port 7 ? av ref1 5 5 ? reference voltage input for d/a converter, positive power supply for port 1 ? av ss 2 2 ? ground potential for a/d and d/a converters (same potential as v ss ) ? 104 124 ? bv dd ? 153 ? positive power supply for bus interface and alternate- function ports ? 103 123 ? bv ss ? 154 ? ground potential for bus interface and alternate- function ports ? clkout 86 106 output internal system clock output pcm1 crxd0 note 1 32 37 p37/ierx0 crxd1 note 2 29 34 input can0, can1 receive data input 5 v tolerant p34/tip10/top10 cs1 82 102 pcs1 cs2 83 103 pcs2 cs3 84 104 output chip select output pcs3 ctxd0 note 1 31 36 p36/ietx0 ctxd1 note 2 28 33 output can0, can1 transmit data output n-ch open-drain output selectable, 5 v tolerant p33/tip01/top01 dck 41 49 input debug clock input, 5 v tolerant p54/sob2/kr4/rtp04 ddi 39 47 input debug data input, 5 v tolerant p52/kr2/tiq03/toq03/rtp02 ddo note 3 40 48 output debug data output n-ch open-drain output selectable, 5 v tolerant p53/sib2/kr3/tiq00/toq00/rtp03 dms 42 50 input debug mode select input, 5 v tolerant p55/sckb2/kr5/rtp05 drst 20 22 input debug reset input, 5 v tolerant p05/intp2 34 39 ? ev dd ? 69 ? positive power supply for external (same potential as v dd ) ? 33 38 ? ev ss ? 70 ? ground potential for external (same potential as v ss ) ? flmd0 8 10 ? flmd1 110 134 input flash memory programming mode setting pin pdl5/ad5 hldak 87 107 output bus hold acknowledge output pcm2 hldrq 88 108 input bus hold request input pcm3 ? 29 p45 note 4 ierx0 32 37 input iebus receive data input, 5 v tolerant p37/crxd0 note 1 ? 28 p44 note 4 ietx0 31 36 output iebus transmit data output n-ch open-drain output selectable, 5 v tolerant p36/ctxd0 note 1 notes 1. can controller version only 2. can controller (2-channel) version only 3. in the on-chip debug mode, high-level output is forcibly set. 4. v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 53 (4/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function intp0 18 20 p03/adtrg intp1 19 21 p04 20 22 p05/drst intp2 24 26 p42/sckb0 intp3 21 23 p06 intp4 74 90 p913/a13 66 82 p95/a5/tip30/top30 intp5 75 91 p914/a14/tip51/top51 ? 96 p153 note 1 intp6 76 92 p915/a15/tip50/top50 26 31 p31/rxda0/sib4 intp7 38 46 p51/kr1/tiq02/toq02/rtp01 59 71 p80/rxda3/rc1ck1hz intp8 note 2 64 80 p93/a3/tip40/top40 49 59 p66/sib5/kr3/tiq00/toq00 intp9 ? 95 input external interrupt request input (maskable, analog noise elimination). analog noise elimination/digital noise elimination selectable for the intp3 pin. 5 v tolerant p152 note 1 kr0 notes 3, 4 37 45 p50/tiq01/toq01/rtp00 kr1 notes 3, 5 38 46 p51/intp7/tiq02/toq02/rtp01 39 47 p52/tiq03/toq03/rtp02/ddi kr2 notes 3, 6 48 58 p65/rtp15/scke1 note 8 /tiq03/toq03 40 48 p53/sib2/tiq00/toq00/rtp03/ ddo kr3 notes 3, 7 49 59 input key interrupt input (on-chip analog noise eliminator) 5 v tolerant p66/sib5/intp9/tiq00/toq00 notes 1. v850e/sk3-h only 2. to use the rxda3 pin and intp8 pin at the same time, use the rxda3 pin at pin 59 and the intp8 pin at pin 64 for the v850e/sj3-h, and use the rxda 3 pin at pin 71 and the intp8 pin at pin 80 for the v850e/sk3-h. in addition, when using the rx da3 pin, always invalidate the edge detection function of the intp8 pin at pin 59 (v85 0e/sj3-h) and pin 71 (v850e/sk3-h). 3. pull this pin up externally. 4. invalidate the edge detection function of the tiq01 pin when using the kr0 pin. 5. invalidate the edge detection function of the tiq02 pin when using the kr1 pin. 6. invalidate the edge detection function of the tiq03 pin when using the kr2 pin. although the kr2 and tiq03 pins are assigned to tw o ports each, the pins cannot be used at the same time at different ports. 7. invalidate the edge detection function of the tiq00 pin when using the kr3 pin. although the kr3 and tiq00 pins are assigned to tw o ports each, the pins cannot be used at the same time at different ports. 8. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 54 (5/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function 41 49 p54/sob2/rtp04/dck kr4 note 1 46 56 p63/rtp13/sie1 note 4 42 50 p55/sckb2/rtp05/dms kr5 note 1 47 57 p64/rtp14/soe1 note 4 kr6 note 1 61 77 p90/a0/txda1/sda02 62 78 p91/a1/rxda1/kr7/scl02 kr7 notes 1, 2 ? 93 input key interrupt input (on-chip analog noise eliminator) 5 v tolerant p150 note 5 /rxda1 note 5 nmi note 3 17 19 input external interrupt input (non-maskable, analog noise elimination) 5 v tolerant p02 rc1ck1hz 59 71 output real-time counter correction clock (1 hz) output n-ch open-drain output selectable 5 v tolerant p80/rxda3/intp8 rc1ckdiv 60 72 output real-time counte r clock (32 khz division) output n-ch open-drain output selectable 5 v tolerant p81/txda3/rc1cko rc1cko 60 72 output real-time counter cloc k (32 khz primary oscillation) output n-ch open-drain output selectable 5 v tolerant p81/txda3/rc1ckdiv rd 99 119 output read strobe signal output for external memory pct4 regc 10 12 ? connection of regulator output stabilization capacitance (4.7 f) ? reset 14 16 input system reset input ? rtp00 37 45 p50/kr0/tiq01/toq01 rtp01 38 46 p51/intp7/kr1/tiq02/toq02 rtp02 39 47 p52/kr2/tiq03/toq03/ddi rtp03 40 48 p53/sib2/kr3/tiq00/toq00/ddo rtp04 41 49 p54/sob2/kr4/dck rtp05 42 50 p55/sckb2/kr5/dms rtp10 43 53 p60/rxda4/sie0 note 4 rtp11 44 54 p61/txda4/soe0 note 4 rtp12 45 55 p62/scke0 note 4 rtp13 46 56 p63/sie1 note 4 /kr4 rtp14 47 57 p64/soe1 note 4 /kr5 rtp15 48 58 output real-time output port n-ch open-drain output selectable 5 v tolerant p65/scke1 note 4 /kr2/tiq03/toq03 notes 1. pull this pin up externally. 2. disable the reception operation of uarta1 when using the kr7 pin. although the kr7 and rxda1 pins are assigned to two ports each, the pins cannot be used at the same time at different ports in the v850e/sk3-h. 3. the nmi pin alternately functions as the p02 pin. it functions as p02 pin after reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1. the initial setti ng of the nmi pin is ?no edge detected?. select the nmi pin valid edge using intf0 and intr0 registers. 4. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) 5. v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 55 (6/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function rxda0 26 31 p31/intp7/sib4 62 78 p91/a1/kr7/kr7/scl02 rxda1 note1 ? 93 p150 note 4 /kr7 note 4 36 41 p39/scl00/sckb2 rxda2 ? 44 p312 note 4 rxda3 note 2 59 71 p80/intp8/rc1ck1hz ? 51 p56 note 4 rxda4 43 53 p60/rtp10/sie0 note 3 50 60 p67/sob5/sda05 note 3 rxda5 ? 75 input serial receive data input (uarta0 to uarta5) 5 v tolerant p84 note 4 rxdb0 77 97 pcd0 rxdb1 79 99 input serial receive data input (uartb0, uartb1) pcd2 sckb0 24 26 p42/intp2 sckb1 70 86 p99/a9 36 41 p39/rxda2/scl00 sckb2 42 50 p55/kr5/rtp05/dms sckb3 73 89 p912/a12 sckb4 27 32 p32/ascka0/tip00/top00 sckb5 51 61 i/o serial clock i/o (csib0 to csib5) n-ch open-drain output selectable 5 v tolerant p68/txda5/scl05 note 3 scke0 note 3 45 55 p62/rtp12 scke1 note 3 48 58 i/o serial clock i/o (csie0, csie1) n-ch open-drain output selectable 5 v tolerant p65/rtp15/kr2/tiq03/toq03 scl00 36 41 p39/rxda2/sckb2 scl01 23 25 p41/sob0 scl02 62 78 p91/a1/kr7/rxda1/kr7 scl03 58 68 p615 7 7 p01/tip60/top60 scl04 note 3 ? 9 i/o serial clock i/o (i 2 c00 to i 2 c05) n-ch open-drain output selectable 5 v tolerant p21 note 4 notes 1. invalidate the key return signal detection function of the kr7 pin w hen using the rxda1 pin. although the rxda1and kr7 pins are assigned to two ports eac h, the pins cannot be us ed at the same time at different ports in the v850e/sk3-h. 2. when using the rxda3 pin, always invalidate the ed ge detection function of the intp8 pin at pin 59 (v850e/sj3-h) and pin 71 (v850e/sk3-h). in this case, use the intp8 pin at pin 64 (v850e/sj3-h) or pin 80 (v850e/sk3-h). 3. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) 4. v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 56 (7/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function 51 61 p68/sckb5/txda5 scl05 note 1 ? 74 i/o serial clock i/o (i 2 c00 to i 2 c05) n-ch open-drain output selectable 5 v tolerant p83 note 2 sda00 35 40 p38/txda2/sib2 sda01 22 24 p40/sib0 sda02 61 77 p90/a0/kr6/txda1 sda03 57 67 p614/tecr8 6 6 p00/tip61/top61 sda04 note 1 ? 8 p20 note 2 50 60 p67/sob5/rxda5 sda05 note 1 ? 73 i/o serial transmit/receive data i/o (i 2 c00 to i 2 c05) n-ch open-drain output selectable 5 v tolerant p82 note 2 sib0 22 24 p40/sda01 sib1 68 84 p97/a7/tip20/top20 35 40 p38/txda2/sda00 sib2 40 48 p53/kr3/tiq00/toq00/rtp03/ddo sib3 71 87 p910/a10 sib4 26 31 p31/rxda0/intp7 sib5 49 59 input serial receive data input (csib0 to csib5) 5 v tolerant p66/intp9/kr3/tiq00/toq00 sie0 note 1 43 53 p60/rtp10/rxda4 sie1 note 1 46 56 input serial receive data input (csie0, csie1) 5 v tolerant p63/rtp13/kr4 sob0 23 25 p41/scl01 sob1 69 85 p98/a8 ? 42 p310 note 2 sob2 41 49 p54/kr4/rtp04/dck sob3 72 88 p911/a11 sob4 25 30 p30/txda0 sob5 50 60 output serial transmit data output (csib0 to csib5) n-ch open-drain output selectable 5 v tolerant p67/rxda5/sda05 note 1 soe0 note 1 44 54 p61/rtp11/txda4 soe1 note 1 47 57 output serial transmit data output (csie0, csie1) n-ch open-drain output selectable 5 v tolerant p64/rtp14/kr5 tecr7 54 64 p611/top71 tecr8 57 67 input encoder clear input (tmp7, tmp8) 5 v tolerant p614/sda03 tenc70 52 62 p69/tip70/top70 tenc71 53 63 p610/tip71 tenc80 55 65 p612/tip80/top80 tenc81 56 66 input encoder input (tmp7, tmp8) 5 v tolerant p613/tip81/top81 notes 1. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) 2. v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 57 (8/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function tip00 27 32 external event count input/capture trigger input/external trigger input (tmp0) 5 v tolerant p32/ascka0/sckb4/top00 tip01 28 33 capture trigger input (tmp0) 5v tolerant p33/top01/ctxd1 note 1 tip10 29 34 external event count input/capture trigger input/external trigger input (tmp1) 5 v tolerant p34/top10/crxd1 note 1 tip11 30 35 capture trigger input (tmp1) 5v tolerant p35/top11 tip20 68 84 external event count input/capture trigger input/external trigger input (tmp2) 5 v tolerant p97/a7/sib1/top20 tip21 67 83 capture trigger input (tmp2) 5 v tolerant p96/a6/top21 tip30 66 82 external event count input/capture trigger input/external trigger input (tmp3) 5 v tolerant p95/a5/top30/intp5 tip31 65 81 capture trigger input (tmp3) 5v tolerant p94/a4/top31 tip40 64 80 external event count input/capture trigger input/external trigger input (tmp4) 5v tolerant p93/a3/top40/intp8 tip41 63 79 capture trigger input (tmp4) 5v tolerant p92/a2/top41 tip50 76 92 external event count input/capture trigger input/external trigger input (tmp5) 5 v tolerant p915/a15/intp6/top50 tip51 75 91 capture trigger input (tmp5) 5v tolerant p914/a14/intp5/top51 tip60 7 7 external event count input/capture trigger input/external trigger input (tmp6) 5 v tolerant p01/top60/scl04 note 2 tip61 6 6 input capture trigger input (tmp6) 5v tolerant p00/top61/sda04 note 2 notes 1. can controller (2-channel) version only 2. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 58 (9/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function tip70 52 62 external event count input/capture trigger input/external trigger input (tmp7) 5 v tolerant p69/top70/tenc70 tip71 53 63 capture trigger input (tmp7) 5v tolerant p610/tenc71 tip80 55 65 external event count input/capture trigger input/external trigger input (tmp8) 5 v tolerant p612/top80/tenc80 tip81 56 66 input capture trigger input (tmp8) 5v tolerant p613/top81/tenc81 40 48 p53/sib2/kr3/toq00/rtp03/ ddo tiq00 note 1 49 59 external event count input/capture trigger input/external trigger input (tmq0) 5v tolerant p66/sib5/intp9/kr3/toq00 tiq01 note 2 37 45 p50/kr0/toq01/rtp00 tiq02 note 3 38 46 p51/intp7/kr1/toq02/rtp01 39 47 p52/kr2/toq03/rtp02/ddi tiq03 note 4 48 58 input capture trigger input (tmq0) 5v tolerant p65/rtp15/scke1/ note 5 kr2/toq03 top00 27 32 p32/ascka0/sckb4/tip00 top01 28 33 timer output (tmp0) n-ch open-drain output selectable, 5 v tolerant p33/tip01/ctxd1 note 6 top10 29 34 p34/tip10/crxd1 note 6 top11 30 35 timer output (tmp1) n-ch open-drain output selectable, 5 v tolerant p35/tip11 top20 68 84 p97/a7/sib1/tip20 top21 67 83 timer output (tmp2) n-ch open-drain output selectable, 5 v tolerant p96/a6/tip21 top30 66 82 p95/a5/tip30/intp5 top31 65 81 timer output (tmp3) n-ch open-drain output selectable, 5 v tolerant p94/a4/tip31 top40 64 80 p93/a3/tip40/intp8 top41 63 79 output timer output (tmp4) n-ch open-drain output selectable, 5 v tolerant p92/a2/tip41 notes 1. invalidate the key return signal detection function of the kr3 pin when using the tiq00 pin. although the tiq00 and kr3 pins are assigned to two ports each, the pins cannot be used at the same time at different ports. 2. invalidate the key return signal detection f unction of the kr0 pin wh en using the tiq01 pin. 3. invalidate the key return signal detection f unction of the kr1 pin wh en using the tiq02 pin. 4. invalidate the key return signal detection func tion of the kr2 pin when using the tiq03 pin. although the tiq03 and kr2 pins are assigned to two ports each, the pins cannot be used at the same time at different ports. 5. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) 6. can controller (2-channel) version only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 59 (10/10) pin no. sj3-h sk3-h pin name gj gm i/o function alternate function top50 76 92 p915/a15/intp6/tip50 top51 75 91 output timer output (tmp5) n-ch open-drain output selectable, 5 v tolerant p914/a14/intp5/tip51 top60 7 7 p01/tip60/scl04 note 1 top61 6 6 timer output (tmp6) n-ch open-drain output selectable, 5 v tolerant p00/tip61/sda04 note 1 top70 52 62 p69/tip70/tenc70 top71 54 64 timer output (tmp7) n-ch open-drain output selectable, 5 v tolerant p611/tecr7 top80 55 65 p612/tip80/tenc80 top81 56 66 output timer output (tmp8) n-ch open-drain output selectable, 5 v tolerant p613/tip81/tenc81 40 48 p53/sib2/kr3/tiq00/rtp03/ddo toq00 49 59 p66/sib5/intp9/kr3/tiq00 toq01 37 45 p50/kr0/tiq01/rtp00 toq02 38 46 p51/intp7/kr1/tiq02/rtp01 39 47 p52/kr2/tiq03/rtp02/ddi toq03 48 58 output timer output (tmq0) n-ch open-drain output selectable, 5 v tolerant p65/rtp15/scke1 note 1 /kr2/tiq03 txda0 25 30 p30/sob4 61 77 p90/a0/kr6/sda02 txda1 ? 94 p151 note 2 35 40 p38/sda00/sib2 txda2 ? 43 p311 note 2 txda3 60 72 p81/rc1cko/rc1ckdiv ? 52 p57 note 2 txda4 44 54 p61/rtp11/soe0 note 1 51 61 p68/sckb5/scl05 note 1 txda5 ? 76 output serial transmit data output (uarta0 to uarta5) n-ch open-drain output selectable, 5 v tolerant p85 note 2 txdb0 78 98 pcd1 txdb1 80 100 output serial transmit data output (uartb0, uartb1) pcd3 v dd 9 11 ? positive power supply pin for internal ? v ss 11 13 ? ground potential for internal ? wait 85 105 input external wait input pcm0 wr0 95 115 write strobe for external memory (lower 8 bits) pct0 wr1 96 116 output write strove for external memory (higher 8 bits) pct1 x1 12 14 input ? x2 13 15 ? connection of resonator for main clock ? xt1 15 17 input ? xt2 16 18 ? connection of resonator for subclock ? notes 1. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) 2. v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 60 2.2 port sharing of alternate functions the v850e/sj3-h and v850e/sk3-h have the same alternate functions that are assigned to two ports. which port is used for the alternate functi on can be selected at the port setup. caution when using an alternate function that is assigned to two ports, always use the alternate function at only one of the ports. chapter 2 pin functions user?s manual u19201ej3v0ud 61 table 2-2. port sharing of alternate functions (1/2) (a) v850e/sj3-h port <1> port <2> function alternate function i/o pin no. port function pin no. port function intp2 20 p05 24 p42 intp5 75 p914 66 p95 intp7 26 p31 38 p51 external interrupt intp8 input 59 p80 64 p93 sib2 input 40 p53 35 p38 csib2 sckb2 i/o 42 p55 36 p39 kr4 41 p54 46 p63 key interrupt kr5 input 42 p55 47 p64 tiq00/kr3 note 1 input 40 p53 49 p66 toq00 output 40 p53 49 p66 tiq03/kr2 note 2 input 39 p52 48 p65 tmq0 (/kr2, /kr3) toq03 output 39 p52 48 p65 notes 1. although the tiq00 and kr3 pins are assigned to two ports each, the pins cannot be used at the same time at different ports. 2. although the tiq03 and kr2 pins are assigned to two ports each, the pins cannot be used at the same time at different ports. chapter 2 pin functions user?s manual u19201ej3v0ud 62 table 2-2. port sharing of alternate functions (2/2) (b) v850e/sk3-h port <1> port <2> function alternate function i/o pin no. port function pin no. port function intp2 22 p05 26 p42 intp5 91 p914 82 p95 intp6 92 p915 96 p153 intp7 31 p31 46 p51 intp8 71 p80 80 p93 external interrupt intp9 input 59 p66 95 p152 scl04 7 p01 9 p21 i 2 c04 sda04 6 p00 8 p20 scl05 61 p68 74 p83 i 2 c05 sda05 i/o 60 p67 73 p82 sib2 input 48 p53 40 p38 sob2 output 49 p54 42 p310 csib2 sckb2 i/o 50 p55 41 p39 rxda1/kr7 note1 input 78 p91 93 p150 uarta1 (/kr7) txda1 output 77 p90 94 p151 rxda2 input 41 p39 44 p312 uarta2 txda2 output 40 p38 43 p311 rxda4 input 53 p60 51 p56 uarta4 txda4 output 54 p61 52 p57 rxda5 input 60 p67 75 p84 uarta5 txda5 output 61 p68 76 p85 ierx0 input 37 p37 29 p45 iebus ietx0 output 36 p36 28 p44 kr4 49 p54 56 p63 key interrupt kr5 input 50 p55 57 p64 tiq00/kr3 note 2 input 48 p53 59 p66 toq00 output 48 p53 59 p66 tiq03/kr2 note 3 input 47 p52 58 p65 tmq0 (/kr2, /kr3) toq03 output 47 p52 58 p65 notes 1. although the rxda1 and kr7 pins are assigned to two ports each, the pins cannot be used at the same time at different ports. 2. although the tiq00 and kr3 pins are assigned to two ports each, the pins cannot be used at the same time at different ports. 3. although the tiq03 and kr2 pins are assigned to two ports each, the pins cannot be used at the same time at different ports. chapter 2 pin functions user?s manual u19201ej3v0ud 63 the following shows a port sharing assignment diagram of alternate functions. figure 2-1. alternate-function port shar ing assignment diagram for v850e/sj3-h (144-pin plastic lqfp (fine pitch) (20 20)) pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0 pcd3/txdb1 pcd2/rxdb1 pcd1/txdb0 pcd0/rxdb0 p915/a15 note 7 /intp6/tip50/top50 p914/a14 note 7 / intp5 /tip51/top51 p913/a13 note 7 /intp4 p912/a12 note 7 /sckb3 av ref0 av ss p10/ano0 p11/ano1 av ref1 p00/tip61/top61/sda04 note 1 p01/tip60/top60/scl04 note 1 flmd0 note 2 v dd regc note 3 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/ intp2 /drst note 4 p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0/ intp2 p30/txda0/sob4 p31/rxda0/ intp7 /sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01/ctxd1 note 5 p34/tip10/top10/crxd1 note 5 p35/tip11/top11 p36/ctxd0 note 6 /ietx0 p37/crxd0 note 6 /ierx0 ev ss ev dd p38/txda2/sda00/ sib2 p39/rxda2/scl00/ sckb2 p50/kr0/tiq01/toq01/rtp00 p51/ intp7 /kr1/tiq02/toq02/rtp01 p52/ kr2/tiq03/toq03 /rtp02/ddi p53/ sib2 / kr3/tiq00/toq00 /rtp03/ddo p54/sob2/ kr4 /rtp04/dck p55/ sckb2 / kr5 /rtp05/dms p60/rtp10/rxda4/sie0 note 1 p61/rtp11/txda4/soe0 note 1 p62/rtp12/scke0 note 1 p63/rtp13/sie1 note 1 / kr4 p64/rtp14/soe1 note 1 / kr5 p65/rtp15/scke1 note 1 / kr2/tiq03/toq03 p66/sib5/intp9 note 1 / kr3/tiq00/toq00 p67/sob5/rxda5/sda05 note 1 p68/sckb5/txda5/scl05 note 1 p69/tip70/top70/tenc70 p610/tip71/tenc71 p611/top71/tecr7 p612/tip80/top80/tenc80 p613/tip81/top81/tenc81 p614/sda03/tecr8 p615/scl03 p80/rxda3/ intp8 /rc1ck1hz p81/txda3/rc1cko/rc1ckdiv p90/a0 note 7 /kr6/txda1/sda02 p91/a1 note 7 /kr7/rxda1/kr7/scl02 p92/a2 note 7 /tip41/top41 p93/a3 note 7 /tip40/top40/ intp8 p94/a4 note 7 /tip31/top31 p95/a5 note 7 /tip30/top30/ intp5 p96/a6 note 7 /tip21/top21 p97/a7 note 7 /sib1/tip20/top20 p98/a8 note 7 /sob1 p99/a9 note 7 /sckb1 p910/a10 note 7 /sib3 p911/a11 note 7 /sob3 p70/ani0 note 8 p71/ani1 note 8 p72/ani2 note 8 p73/ani3 note 8 p74/ani4 note 8 p75/ani5 note 8 p76/ani6 note 8 p77/ani7 note 8 p78/ani8 note 8 p79/ani9 note 8 p710/ani10 note 8 p711/ani11 note 8 p712/ani12 note 8 p713/ani13 note 8 p714/ani14 note 8 p715/ani15 note 8 pdh7/a23 pdh6/a22 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 remark the above figure shows the assignment relationship of the same alternate function that is assigned to two ports. chapter 2 pin functions user?s manual u19201ej3v0ud 64 figure 2-2 alternate-function port sharing assignment diagram for v850e/sk3-h (176-pin plastic lqfp (fine pitch) (24 24)) 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 p133 p132 p131 p130 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0 pcd3/txdb1 pcd2/rxdb1 pcd1/txdb0 pcd0/rxdb0 p153/ intp6 p152/ intp9 p151/ txda1 p150/ rxda1/kr7 p915/a15 note 6 intp6 /tip50/top50 p914/a14 note 6 / intp5 /tip51/top51 p913/a13 note 6 /intp4 p912/a12 note 6 /sckb3 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 p70/ani0 note 7 p71/ani1 note 7 p72/ani2 note 7 p73/ani3 note 7 p74/ani4 note 7 p75/ani5 note 7 p76/ani6 note 7 p77/ani7 note 7 p78/ani8 note 7 p79/ani9 note 7 p710/ani10 note 7 p711/ani11 note 7 p712/ani12 note 7 p713/ani13 note 7 p714/ani14 note 7 p715/ani15 note 7 p145 p144 p143 p142 p141 p140 bv ss bv dd pdh7/a23 pdh6/a22 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 p50/kr0/tiq01/toq01/rtp00 p51/ intp7 /kr1/tiq02/toq02/rtp01 p52/ kr2/tiq03/toq03 /rtp02/ddi p53/ sib2 / kr3/tiq00/toq00 /rtp03/ddo p54/ sob2 / kr4 /rtp04/dck p55/ sckb2 / kr5 /rtp05/dms p56/ rxda4 p57/ txda4 p60/rtp10/ rxda4 /sie0 p61/rtp11/ txda4 /soe0 p62/rtp12/scke0 p63/rtp13/sie1/ kr4 p64/rtp14/soe1/ kr5 p65/rtp15/scke1/ kr2/tiq03/toq03 p66/sib5/ intp9 / kr3/tiq00/toq00 p67/sob5/ rxda5 / sda05 p68/sckb5/ txda5 / scl05 p69/tip70/top70/tenc70 p610/tip71/tenc71 p611/top71/tecr7 p612/tip80/top80/tenc80 p613/tip81/top81/tenc81 p614/sda03/tecr8 p615/scl03 ev dd ev ss p80/rxda3/ intp8 /rc1ck1hz p81/txda3/rc1cko/rc1ckdiv p82/ sda05 p83/ scl05 p84/ rxda5 p85/ txda5 p90/a0 note 6 /kr6/ txda1 /sda02 p91/a1 note 6 / kr7/rxda1/kr7 /scl02 p92/a2 note 6 /tip41/top41 p93/a3 note 6 /tip40/top40/ intp8 p94/a4 note 6 /tip31 /top31 p95/a5 note 6 /tip30/top30/ intp5 p96/a6 note 6 / tip21/top21 p97/a7 note 6 /sib1/tip20/top20 p98/a8 note 6 /sob1 p99/a note 6 /sckb1 p910/a10 note 6 /sib3 p911/a11 note 6 /sob3 av ref0 av ss p10/ano0 p11/ano1 av ref1 p00/tip61/top61/ sda04 p01/tip60/top60/ scl04 p20/ sda04 p21/ scl04 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/ intp2 /drst note 3 p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0/ intp2 p43 p44/ ietx0 p45/ ierx0 p30/txda0/sob4 p31/rxda0/ intp7 /sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01/ctxd1 note 4 p34/tip10/top10/crxd1 note 4 p35/tip11/top11 p36/ctxd0 note 5 / ietx0 p37/crxd0 note 5 / ierx0 ev ss ev dd p38/ txda2 /sda00/ sib2 p39/ rxda2 /scl00/ sckb2 p310/ sob2 p311/ txda2 p312/ rxda2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 remark the above figure shows the assignment relationship of the same alternate function that is assigned to two ports. chapter 2 pin functions user?s manual u19201ej3v0ud 65 2.3 pin states the operation states of pins in the vari ous operation modes are described below. table 2-3. pin operation states in various modes pin name during reset (immediately after power is turned on) during reset (except immediately after power is turned on) halt mode note 2 idle1, idle2, sub-idle mode note 2 stop mode note 2 idle state note 3 bus hold p05/drst pull down pull down note 4 held held held held held p10/ano0, p11/ano1 hi-z hi-z held held note 10 held held p53/ddo undefined note 1 hi-z note 5 held held held held held ad0 to ad15 notes 7, 8 a0 to a15 undefined notes 7, 9 a16 to a23 undefined note 7 hi-z hi-z held hi-z wait ? ? ? ? ? clkout operating l l operating operating wr0, wr1 rd astb h note 7 hi-z hldak h h h l hldrq operating note 7 ? ? ? held cs1 to cs3 hi-z note 6 hi-z note 6 h note 7 h h h hi-z other port pins hi-z hi-z held held held held held notes 1. these pins may momentarily output an un defined level upon power application. 2. operates while alternat e functions are operating. 3. in separate bus mode, the state of the pins in the idle state inserted after the t2 state is shown. in multiplexed bus mode, the state of the pins in the idle state inserted after the t3 state is shown. 4. pulled down during external reset. during internal reset by the watchdog timer, low-voltage detector, or clock monitor, etc., the state of this pin di ffers according to the ocdm.ocdm0 bit setting. 5. ddo output is specified in the on-chip debug mode. 6. the bus control pins function alternately as port pi ns, so they are initialized to the input mode (port mode). 7. operates even in the halt mode, during dma operation. 8. in separate bus mode: hi-z in multiplexed bus mode: undefined 9. in separate bus mode 10. in port mode: held when alternate function is used: hi-z remark hi-z: high impedance held: the state during the immediately preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged) chapter 2 pin functions user?s manual u19201ej3v0ud 66 2.4 pin i/o circuit types, i/o buffer power supplies and connection of unused pins (1/6) pin no. sj3-h sk3-h pin alternate function gj gm i/o circuit type recommended connection p00 tip61/top61/sda04 note 2 6 6 p01 tip60/top60/scl04 note 2 7 7 p02 nmi 17 19 p03 intp0/adtrg 18 20 p04 intp1 19 21 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p05 intp2/drst 20 22 10-n input: independently connect to ev ss via a resistor. fixing to v dd level is prohibited. output: leave open. internally pull-down after reset by reset pin. p06 intp3 21 23 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p10 ano0 3 3 p11 ano1 4 4 12-d input: independently connect to av ref1 or av ss via a resistor. output: leave open. p20 note 1 sda04 ? 8 p21 note 1 scl04 ? 9 10-d p30 txda0/sob4 25 30 10-g p31 rxda0/intp7/sib4 26 31 p32 ascka0/sckb4/tip00/ top00 27 32 p33 tip01/top01/ctxd1 note 3 28 33 p34 tip10/top10/crxd1 note 3 29 34 p35 tip11/top11 30 35 10-d p36 ctxd0 note 4 /ietx0 31 36 10-g p37 crxd0 note 4 /ierx0 32 37 p38 txda2/sda00/sib2 35 40 p39 rxda2/scl00/sckb2 36 41 10-d p310 note 1 sob2 note 1 ? 42 p311 note 1 txda2 note 1 ? 43 10-g p312 note 1 rxda2 note 1 ? 44 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes 1. v850e/sk3-h only 2. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) 3. can controller (2-channel) version only 4. can controller version only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 67 (2/6) pin no. sj3-h sk3-h pin alternate function gj gm i/o circuit type recommended connection p40 sib0/sda01 22 24 p41 sob0/scl01 23 25 p42 sckb0/intp2 24 26 10-d p43 note 1 ? ? 27 p44 note 1 ietx0 note 1 ? 28 10-g p45 note 1 ierx0 note 1 ? 29 p50 kr0/tiq01/toq01/rtp00 37 45 p51 intp7/kr1/tiq02/toq02/ rtp01 38 46 p52 kr2/tiq03/toq03/rtp02/ ddi 39 47 p53 sib2/kr3/tiq00/toq00/ rtp03/ddo 40 48 p54 sob2/kr4/rtp04/dck 41 49 p55 sckb2/kr5/rtp05/dms 42 50 p56 note 1 rxda4 note 1 ? 51 10-d p57 note 1 txda4 note 1 ? 52 10-g p60 rtp10/rxda4/sie0 note 2 43 53 10-d p61 rtp11/txda4/soe0 note 2 44 54 10-g p62 rtp12/scke0 note 2 45 55 p63 rtp13/sie1 note 2 /kr4 46 56 p64 rtp14/soe1 note 2 /kr5 47 57 p65 rtp15/scke1 note 2 /kr2/ tiq03/toq03 48 58 p66 sib5/intp9/kr3/tiq00/ toq00 49 59 p67 sob5/rxda5/sda05 note 2 50 60 p68 sckb5/txda5/scl05 note 2 51 61 p69 tip70/top70/tenc70 52 62 p610 tip71/tenc71 53 63 p611 top71/tecr7 54 64 p612 tip80/top80/tenc80 55 65 p613 tip81/top81/tenc81 56 66 p614 sda03/tecr8 57 67 p615 scl03 58 68 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes 1. v850e/sk3-h only 2. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3- h) remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 68 (3/6) pin no. sj3-h sk3-h pin alternate function gj gm i/o circuit type recommended connection p70 ani0 144 176 p71 ani1 143 175 p72 ani2 142 174 p73 ani3 141 173 p74 ani4 140 172 p75 ani5 139 171 p76 ani6 138 170 p77 ani7 137 169 p78 ani8 136 168 p79 ani9 135 167 p710 ani10 134 166 p711 ani11 133 165 p712 ani12 132 164 p713 ani13 131 163 p714 ani14 130 162 p715 ani15 129 161 11-g input: independently connect to av ref0 or av ss via a resistor. output: leave open. p80 rxda3/intp8/rc1ck1hz 59 71 10-d p81 txda3/rc1cko/rc1ckdiv 60 72 10-g p82 note sda05 note ? 73 p83 note scl05 note ? 74 p84 note rxda5 note ? 75 10-d p85 note txda5 note ? 76 10-g p90 a0/kr6/txda1/sda02 61 77 p91 a1/kr7/rxda1/kr7/scl02 62 78 p92 a2/tip41/top41 63 79 p93 a3/tip40/top40/intp8 64 80 p94 a4/tip31/top31 65 81 p95 a5/tip30/top30/intp5 66 82 p96 a6/tip21/top21 67 83 p97 a7/sib1/tip20/top20 68 84 10-d p98 a8/sob1 69 85 10-g p99 a9/sckb1 70 86 p910 a10/sib3 71 87 10-d p911 a11/sob3 72 88 10-g input: independently connect to ev dd or ev ss via a resistor. output: leave open. note v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 69 (4/6) pin no. sj3-h sk3-h pin alternate function gj gm i/o circuit type recommended connection p912 a12/sckb3 73 89 p913 a13/intp4 74 90 p914 a14/intp5/tip51/top51 75 91 p915 a15/intp6/tip50/top50 76 92 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p130 note ? ? 125 p131 note ? ? 126 p132 note ? ? 127 p133 note ? ? 128 p140 note ? ? 155 p141 note ? ? 156 p142 note ? ? 157 p143 note ? ? 158 p144 note ? ? 159 p145 note ? ? 160 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. p150 note rxda1 note /kr7 note ? 93 10-d p151 note txda1 note ? 94 10-g p152 note intp9 note ? 95 p153 note intp6 note ? 96 input: independently connect to ev dd or ev ss via a resistor. output: leave open. pcd0 rxdb0 77 97 10-d pcd1 txdb0 78 98 10-g pcd2 rxdb1 79 99 10-d pcd3 txdb1 80 100 10-g pcm0 wait 85 105 pcm1 clkout 86 106 pcm2 hldak 87 107 pcm3 hldrq 88 108 pcm4 ? 89 109 pcm5 ? 90 110 pcs0 ? 81 101 pcs1 cs1 82 102 pcs2 cs2 83 103 pcs3 cs3 84 104 pcs4 ? 91 111 pcs5 ? 92 112 pcs6 ? 93 113 pcs7 ? 94 114 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. note v850e/sk3-h only remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 70 (5/6) pin no. sj3-h sk3-h pin alternate function gj gm i/o circuit type recommended connection pct0 wr0 95 115 pct1 wr1 96 116 pct2 ? 97 117 pct3 ? 98 118 pct4 rd 99 119 pct5 ? 100 120 pct6 astb 101 121 pct7 ? 102 122 pdh0 a16 121 145 pdh1 a17 122 146 pdh2 a18 123 147 pdh3 a19 124 148 pdh4 a20 125 149 pdh5 a21 126 150 pdh6 a22 127 151 pdh7 a23 128 152 pdl0 ad0 105 129 pdl1 ad1 106 130 pdl2 ad2 107 131 pdl3 ad3 108 132 pdl4 ad4 109 133 input: independently connect to bv dd or bv ss via a resistor. output: leave open. pdl5 ad5/flmd1 110 134 independently connect to bv ss via a resistor. pdl6 ad6 111 135 pdl7 ad7 112 136 pdl8 ad8 113 137 pdl9 ad9 114 138 pdl10 ad10 115 139 pdl11 ad11 116 140 pdl12 ad12 117 141 pdl13 ad13 118 142 pdl14 ad14 119 143 pdl15 ad15 120 144 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 71 (6/6) pin no. sj3-h sk3-h pin alternate function gj gm i/o circuit type recommended connection av ref0 ? 1 1 av ref1 ? 5 5 ? always connect this pin to the power supply (also in the standby mode). av ss ? 2 2 ? always connect this pin directly to the ground (also in the standby mode). ? 104 124 bv dd ? ? 153 ? always connect this pin to the power supply (also in the standby mode). ? 103 123 bv ss ? ? 154 ? always connect this pin directly to the ground (also in the standby mode). ? 34 39 ev dd ? ? 69 ? always connect this pin directly to the power supply (also in the standby mode). ? 33 38 ev ss ? ? 70 ? always connect this pin directly to the ground (also in the standby mode). flmd0 ? 8 10 ? connect to v ss in a mode other than the flash memory programming mode. regc ? 10 12 ? connect regulator output stabilization capacitance (4.7 f) reset ? 14 16 2 ? v dd ? 9 11 ? always connect this pin to the power supply (also in the standby mode). v ss ? 11 13 ? always connect this pin directly to the ground (also in the standby mode). x1 ? 12 14 ? ? x2 ? 13 15 ? ? xt1 ? 15 17 connect to v ss . xt2 ? 16 18 16-c leave open. remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 2 pin functions user?s manual u19201ej3v0ud 72 figure 2-3. pin i/o circuits type 2 type 5 in data output disable p-ch in/out bv dd bv ss n-ch input enable type 11-g type 12-d type 10-d data output disable ev dd ev ss p-ch in/out in/out n-ch open drain input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch av ref0 input enable comparator + _ av ss av ss data output disable input enable av ref1 p-ch in/out n-ch p-ch n-ch analog output voltage av ss type 10-n data output disable ev dd ev ss p-ch in/out n-ch open drain input enable ocdm0 bit n-ch type 16-c type 10-g data output disable ev dd ev ss p-ch in/out n-ch open drain input enable p-ch feedback cut-off xt1 xt2 schmitt-triggered input with hysteresis characteristics note note (threshold voltage) note hysteresis characteristics are not available in port mode. chapter 2 pin functions user?s manual u19201ej3v0ud 73 2.5 cautions (1) cautions on power application when the power is turned on, the following pins may momentarily output an undefined level. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin user?s manual u19201ej3v0ud 74 chapter 3 cpu function the cpu of the v850e/sj3-h and v850e/sk3-h is bas ed on risc architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time : 20.8 ns (operating with 48 mhz) 30.5 s (operating with subclock (f xt ) = 32.768 khz operation) memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 chapter 3 cpu function user?s manual u19201ej3v0ud 75 3.2 cpu register set the registers of the v850e/sj3-h an d v850e/sk3-h can be classified into two types: general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850e1 architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) asid (program id register) chapter 3 cpu function user?s manual u19201ej3v0ud 76 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these in structions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. general-purpose registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that i ndicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function remark for furthers details on the r1, r3 to r5, and r31 that are used in the assembler and c compiler, refer to the ca850 (c compiler package) a ssembly language user?s manual . (2) program counter (pc) the program counter holds the instructio n address during program execution. the lower 26 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h chapter 3 cpu function user?s manual u19201ej3v0ud 77 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/store instructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification system register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) note 1 3 nmi status saving register (fepsw) note 1 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21, 22 reserved for future function expansi on (operations that access these register numbers cannot be guaranteed). 23 program id register (asid) 24 to 31 reserved for future function expansi on (operations that access these register numbers cannot be guaranteed). notes 1. because only one set of these registers is availabl e, the contents of these r egisters must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only during th e interval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. caution even if eipc or fepc, or bit 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt ser vicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited chapter 3 cpu function user?s manual u19201ej3v0ud 78 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, the contents of the program counter (pc) are saved to eipc, and the contents of the program status word ( psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and f epsw) if a non-maskable interrupt occurs). the address of the instruction next to the instruction under execution, except some instructions (see 24.8 periods in which interrupts are not acknowledged by cpu ), is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved for future function expansion (these bits are always fixed to 0). the value of eipc is restored to the pc and the val ue of eipsw to the psw by the reti instruction. 31 0 eipc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function user?s manual u19201ej3v0ud 79 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the program counter (pc) are saved to fepc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to the one of the instruction under execut ion, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. because only one set of nmi status saving registers is avai lable, the contents of thes e registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). the value of fepc is restored to the pc and the value of fepsw to the psw by the reti instruction. 31 0 fepc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) hol ds the source of an exception or in terrupt if an exception or interrupt occurs. this register holds the exc eption code of each interrupt source. be cause this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt chapter 3 cpu function user?s manual u19201ej3v0ud 80 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate th e status of the program (result of instruction execution) and the status of the cpu. if the contents of a bit of this regi ster are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instructi on execution. however if the id flag is set to 1, interrupt requests will not be acknowledged while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name function 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being proces sed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a ca rry or a borrow occurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page. chapter 3 cpu function user?s manual u19201ej3v0ud 81 (2/2) note the result of the operation that has performed satu ration processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execution status saving registers. when the callt instruction is execut ed, the contents of the program count er (pc) are saved to ctpc, and those of the program status wo rd (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function user?s manual u19201ej3v0ud 82 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of th e instruction next to the one that is being executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. this register can be read or written only during the in terval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). the value of dbpc is restored to the pc and the value of dbpsw to the psw by the dbret instruction. 31 0 dbpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a table address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 chapter 3 cpu function user?s manual u19201ej3v0ud 83 (8) program id register (asid) asid sets the id of the program in progress. bits 31 to 8 of this register are reserved for future function expansion (fixed to 0). caution to use the v850e/sj3-h or v850e/sk3-h, initializ e the asid register to 00h in its initialization routine. 31 0 7 8 asid asid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 after reset 000000xxh (x: undefined) bit position flag name function 7 to 0 asid id of program under execution chapter 3 cpu function user?s manual u19201ej3v0ud 84 3.3 operation modes the v850e/sj3-h and v850e/sk3-h ha ve the following operation modes. (1) normal operation mode in this mode, each pin related to the bus interface is set to the port mode after system reset has been released. execution branches to the reset entry address of the intern al rom, and then instruction processing is started. (2) flash memory programming mode in this mode, the internal flash memory can be programmed by using a flash memory programmer. (3) on-chip debug mode the v850e/sj3-h and v850e/sk3-h are provided with an on-chip debug function that employs the jtag (joint test action group) communicat ion specifications and that is exec uted via an on-chip debug emulator. for details, see chapter 34 on-chip debug function . 3.3.1 specifying operation mode specify the operation mode by using the flmd0 and flmd1 pins. in the normal mode, input a low level to the flmd0 pin when reset is released. in the flash memory programming mode, a high level is in put to the flmd0 pin from the flash memory programmer if a flash memory programmer is connected, but it must be input from an external circuit in the self-programming mode. operation when reset is released flmd0 flmd1 operation mode after reset l normal operation mode h l flash memory programming mode h h setting prohibited remark l: low-level input h: high-level input : don?t care chapter 3 cpu function user?s manual u19201ej3v0ud 85 3.4 address space 3.4.1 cpu address space for instruction addressing, up to a combined total of 32 mb of external memory area and internal rom area, plus an internal ram area, are supported in a linear addres s space (program space) of up to 64 mb. for operand addressing (data access), up to 4 gb of a linear address s pace (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical a ddress space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. image on address space use-prohibited area external memory area use-prohibited area use-prohibited area expanded internal ram area or external memory area expanded internal ram area or external memory area program space internal ram area use-prohibited area use-prohibited area internal rom area data space image 63 image 1 image 0 on-chip peripheral i/o area internal ram area programmable peripheral i/o area or use-prohibited area external memory area internal rom area 32 mb 4 gb 64 mb 64 mb . . . caution only the programmable peripheral i/o area can be viewed in the 4 gb address space as the image in 256 mb unit. chapter 3 cpu function user?s manual u19201ej3v0ud 86 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the highest address of the program space, 03ffffffh, and the lowest address, 00000000h, are contiguous addresses. that the highest address and t he lowest address of the pr ogram space are contiguous in this way is called wraparound. caution because the 4 kb area of addresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetc hed from this area. therefore, do not execute an operation in which the result of a branch addr ess calculation affects this area. program space program space (+) direction ( ? ) direction 00000001h 00000000h 03ffffffh 03fffffeh (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the highest address of the data space, ffffffffh, and the lowest address, 00000000h, are contiguous, and wraparound occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction 00000001h 00000000h ffffffffh fffffffeh chapter 3 cpu function user?s manual u19201ej3v0ud 87 3.4.3 memory map the areas shown below are reserved in the v850e/sj3-h and v850e/sk3-h. figure 3-2. data memory map (physical addresses) (1/2) (a) when using expanded internal ram (80 kb) use prohibited external memory area (28 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use prohibited note 1 internal rom area (4 mb) 03ffffffh 03fec000h 02000000h 01ffffffh 00400000h 003fffffh 00000000h 03febfffh 03ffffffh 03fff000h 03ffefffh 03ff0000h 03feffffh programmable peripheral i/o area note 2 or use prohibited note 3 03fef000h 03feefffh 03fec000h 03fe4000h 03fe3fffh expanded internal ram area (32 kb max.) notes 1. use of addresses 03fef000h to 03feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. only the programmable peripheral i/o area can be viewed in the 4 gb address space as t he image in 256 mb unit. 3. addresses 03fec000h to 03fecbffh are alloca ted to addresses 03fec000h to 03feefffh of the can controller version as a programmable per ipheral i/o area. use of these addresses in a version without a can controller is prohibited. chapter 3 cpu function user?s manual u19201ej3v0ud 88 figure 3-2. data memory map (physical addresses) (2/2) (b) when not using expanded internal ram (80 kb) use prohibited external memory area (28 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use prohibited note 1 internal rom area (4 mb) 03ffffffh 03fec000h 02000000h 01ffffffh 00400000h 003fffffh 00000000h 03febfffh 03ffffffh 03fff000h 03ffefffh 03ff0000h 03feffffh programmable peripheral i/o area note 2 or use prohibited note 3 03fef000h 03feefffh 03fec000h 03e00000h 03dfffffh external memory area (1968 kb) notes 1. use of addresses 03fef000h to 03feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. only the programmable peripheral i/o area can be viewed in the 4 gb address space as t he image in 256 mb unit. 3. addresses 03fec000h to 03feefffh are alloca ted to addresses 03fec000h to 03fecbffh of the can controller version as a programmable per ipheral i/o area. use of these addresses in a version without a can controller is prohibited. chapter 3 cpu function user?s manual u19201ej3v0ud 89 figure 3-3. program memory map (1/2) (a) when using expanded internal ram internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area (28 mb) internal rom area (4 mb) 03ffffffh 03fff000h 03ffefffh 03fe4000h 03fe3fffh 03ff0000h 03feffffh 02000000h 01ffffffh 00400000h 003fffffh 00000000h 03fec000h 03febfffh use prohibited (program fetch prohibited area) expanded internal ram area (32 kb max.) chapter 3 cpu function user?s manual u19201ej3v0ud 90 figure 3-3. program memory map (2/2) (b) when not using expanded internal ram internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area (28 mb) internal rom area (4 mb) 03ffffffh 03fff000h 03ffefffh 03e00000h 03dfffffh 03ff0000h 03feffffh 02000000h 01ffffffh 00400000h 003fffffh 00000000h 03fec000h 03febfffh use prohibited (program fetch prohibited area) external memory area (1968 kb) chapter 3 cpu function user?s manual u19201ej3v0ud 91 3.4.4 areas (1) internal rom area up to 4 mb is reserved as an internal rom area. (a) internal rom (512 kb) 512 kb are allocated to addre sses 00000000h to 0007ffffh in the following versions. accessing addresses 00080000h to 003fffffh is prohibited. ? pd70f3931 (v850e/sj3-h), 70f3932 (v85 0e/sj3-h), 70f3933 (v850e/sj3-h) figure 3-4. internal rom area (512 kb) access-prohibited area internal rom (512 kb) 00080000h 0007ffffh 00000000h 003fffffh chapter 3 cpu function user?s manual u19201ej3v0ud 92 (b) internal rom (768 kb) 768 kb are allocated to addresses 00000000h to 000bffffh in the following versions. accessing addresses 000c0000h to 003fffffh is prohibited. ? pd70f3934 (v850e/sj3-h), 70f3935 (v85 0e/sj3-h), 70f3936 (v850e/sj3-h) figure 3-5. internal rom area (768 kb) access-prohibited area internal rom (768 kb) 000c0000h 000bffffh 00000000h 003fffffh (c) internal rom (1024 kb) 1024 kb are allocated to addre sses 00000000h to 000fffffh in the following versions. accessing addresses 00100000h to 003fffffh is prohibited. ? pd70f3925 (v850e/sk3-h), 70f3926 (v850e /sk3-h), 70f3927 (v850e/sk3-h), 70f3937 (v850e/sj3-h), 70f3938 (v8 50e/sj3-h), 70f3939 (v850e/sj3-h) figure 3-6. internal rom area (1024 kb) access-prohibited area internal rom (1024 kb) 00100000h 000fffffh 00000000h 003fffffh chapter 3 cpu function user?s manual u19201ej3v0ud 93 (d) internal rom (1280 kb) 1280 kb are allocated to addre sses 00000000h to 0013ffffh in the following versions. accessing addresses 00140000h to 003fffffh is prohibited. ? pd70f3474 (v850e/sj3-h), 70f3475 (v850e /sj3-h), 70f3476 (v850e/sj3-h), 70f3486 (v850e/sk3-h), 70f3487 (v8 50e/sk3-h), 70f3488 (v850e/sk3-h) figure 3-7. internal rom area (1280 kb) access-prohibited area internal rom (1280 kb) 00140000h 0013ffffh 00000000h 003fffffh (e) internal rom (1536 kb) 1536 kb are allocated to addre sses 00000000h to 0017ffffh in the following versions. accessing addresses 00180000h to 003fffffh is prohibited. ? pd70f3477 (v850e/sj3-h), 70f3478 (v850e /sj3-h), 70f3479 (v850e/sj3-h), 70f3480 (v850e/sk3-h), 70f3481 (v8 50e/sk3-h), 70f3482 (v850e/sk3-h) figure 3-8. internal rom area (1536 kb) access-prohibited area internal rom (1536 kb) 00180000h 0017ffffh 00000000h 003fffffh chapter 3 cpu function user?s manual u19201ej3v0ud 94 (2) internal ram area 60 kb are allocated to addresses 03ff0000h to 03ffefffh in the internal ram area. figure 3-9. internal ram area (60 kb) internal ram (60 kb) 03ff0000h 03ffefffh physical address space logical address space ffff0000h ffffefffh chapter 3 cpu function user?s manual u19201ej3v0ud 95 (3) on-chip peripheral i/o area 4 kb of addresses 03fff000h to 03ffffffh are re served as the on-chip peripheral i/o area. figure 3-10. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 03ffffffh 03fff000h ffffffffh fffff000h physical address space logical address space peripheral i/o registers that have functions to specif y the operation mode for and mo nitor the status of the on- chip peripheral i/o are mapped to the on-chip periphe ral i/o area. program cannot be fetched from this area. cautions 1. when a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read , and data is written to the lower 8 bits. 3. addresses not defined as registers are r eserved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. 4. the internal rom/ram area and on-chip peripheral i/o area are assigned to successive addresses. when accessing the in ternal rom/ram area by in crementing or decrementing addresses using pointer operations and such, therefore, be careful not to access the on- chip peripheral i/o area by mistakenly ex tending over the internal rom/ram area boundary. (4) programmable peripheral i/o area cautions 1. the programmable peripheral i/o area exists only in the can controller versions. this area cannot be used with products that are not equipped with the can controller. 2. only the programmable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. 12 kb of addresses 03fec000h to 03feefffh are rese rved as the programmable peripheral i/o area. figure 3-11. programmable peripheral i/o area programmable peripheral i/o area (12 kb) 03feefffh 03fec000h chapter 3 cpu function user?s manual u19201ej3v0ud 96 (5) external memory area up to 30 mb (00400000h to 01ffffffh , 03e00000h to 03febfffh) are alloca ted as the external memory area. for details, see chapter 5 bus control function . (6) expanded internal ram area the 32 kb area from addresses 03fe4000h to 03febfff h is reserved as an expanded internal ram area. the expanded internal ram area is accessed via the external bus interface. before accessing the expanded internal ram area, be sure to set the registers relate d to the external bus interface (initialization of the expanded internal ram). remarks 1. the following products are not provided with expanded internal ram. ? pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), 70f3933 (v850e/sj3-h) 2. expanded internal ram area can be used as external memory area. for details, see chapter 5 bus control function . cautions 1. when using the exte rnal memory and expanded intern al ram simultaneously, set the external bus interface and expanded internal ram at the same time. 2. when accessing the expanded internal ram, a ll the external bus interface control signals except the csn signal become active (n = 1 to 3). therefore, when using the expanded internal ram and external memory at the same time, be sure to control access to the external memory by using the csn signal output from the chip. 3. if an external wait is inser ted via the wait pin, an external wait will also be inserted into expanded internal ram access. 4. be sure to specify the initial settings for the expanded internal ram before using it. (a) expanded internal ram (16 kb) 16 kb are allocated to addres ses 03fe8000h to 03febfffh in the following versions. accessing addresses 03fe4000h to 03fe7fffh is prohibited. ? pd70f3925 (v850e/sk3-h), 70f3926 (v850e /sk3-h), 70f3927 (v850e/sk3-h), 70f3934 (v850e/sj3-h), 70f3935 (v850e /sj3-h), 70f3936 (v850e/sj3-h), 70f3937 (v850e/sj3-h), 70f3938 (v8 50e/sj3-h), 70f3939 (v850e/sj3-h) figure 3-12. expanded internal ram area (16 kb) physical address space logical address space expanded internal ram (16 kb) access-prohibited area 03febfffh 03fe8000h 03fe7fffh 03fe4000h fffebfffh fffe8000h fffe7fffh fffe4000h chapter 3 cpu function user?s manual u19201ej3v0ud 97 (b) expanded internal ram (32 kb) 32 kb are allocated to addres ses 03fe4000h to 03febfffh in the following versions. ? pd70f3474 (v850e/sj3-h), 70f3475 (v850e /sj3-h), 70f3476 (v850e/sj3-h), 70f3477 (v850e/sj3-h), 70f3478 (v850e /sj3-h), 70f3479 (v850e/sj3-h), 70f3480 (v850e/sk3-h), 70f3481 (v850e /sk3-h), 70f3482 (v850e/sk3-h), 70f3486 (v850e/sk3-h), 70f3487 (v8 50e/sk3-h), 70f3488 (v850e/sk3-h) figure 3-13. expanded internal ram area (32 kb) expanded internal ram area (32 kb) physical address space logical address space 03febfffh 03fe4000h fffebfffh fffe4000h (c) features of expanded internal ram ? can be accessed in as few as three bus cycles ? 32-bit data bus ? misaligned access possible chapter 3 cpu function user?s manual u19201ej3v0ud 98 (d) initial settings for expanded internal ram the initial settings for the expanded internal ram are shown below. caution if the expanded internal ram is used wi th any but the following initial settings, operation is not guaranteed. ? bsc register setting bits 15 to 8 must be set to 10010101. ? dwc1 register setting set the values of the dwc1 register as follows, in accordance with the setting of the eximc register. eximc register setting dwc1 register setting 00h (multiplexed bus mode) 0777h 01h (separate bus mode) 1777h ? awc register setting bits 15 to 8 must be set to 00111111. ? bcc register setting bits 15 to 8 must be set to 00101010. chapter 3 cpu function user?s manual u19201ej3v0ud 99 (7) product selection register (prdsel) the prdsel register is a register to identif y the product name and the internal ram area. this register is used divided into two 16-bit registers, prdselh and prdsell. this register is read-only, in 16-bit units. ram3 to ram0 1010 note 1 1011 note 2 ram start address after reset: depends on product r address: prdsell fffffcc8h, prdselh fffffccah product name (last 3 digits) prdselh prdsell ram3 ram2 ram1 ram0 03ff0000h notes 1. pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3 -h), and 70f3933 (v850e/sj3-h) only 2. other than pd70f3931 (v850e/sj3-h), 70f39 32 (v850e/sj3-h), and 70f3933 (v850e/sj3-h) caution this register cannot be read by th e in-circuit emulator (qb-v850esx3h) (an undefined value is read). remarks 1. see table 3-3 for product name setting examples. 2. x: undefined value table 3-3. product name setting examples (1/2) prdsell register product name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 pd70f3 474 0 1 0 0 0 1 1 1 0 1 0 0 pd70f3 475 0 1 0 0 0 1 1 1 0 1 0 1 pd70f3 476 0 1 0 0 0 1 1 1 0 1 1 0 pd70f3 477 0 1 0 0 0 1 1 1 0 1 1 1 pd70f3 478 0 1 0 0 0 1 1 1 1 0 0 0 pd70f3 479 0 1 0 0 0 1 1 1 1 0 0 1 pd70f3 480 0 1 0 0 1 0 0 0 0 0 0 0 pd70f3 481 0 1 0 0 1 0 0 0 0 0 0 1 pd70f3 482 0 1 0 0 1 0 0 0 0 0 1 0 pd70f3 486 0 1 0 0 1 0 0 0 0 1 1 0 pd70f3 487 0 1 0 0 1 0 0 0 0 1 1 1 pd70f3 488 0 1 0 0 1 0 0 0 1 0 0 0 pd70f3 925 1 0 0 1 0 0 1 0 0 1 0 1 pd70f3 926 1 0 0 1 0 0 1 0 0 1 1 0 pd70f3 927 1 0 0 1 0 0 1 0 0 1 1 1 chapter 3 cpu function user?s manual u19201ej3v0ud 100 table 3-3. product name setting examples (2/2) prdsell register product name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 pd70f3 931 1 0 0 1 0 0 1 1 0 0 0 1 pd70f3 932 1 0 0 1 0 0 1 1 0 0 1 0 pd70f3 933 1 0 0 1 0 0 1 1 0 0 1 1 pd70f3 934 1 0 0 1 0 0 1 1 0 1 0 0 pd70f3 935 1 0 0 1 0 0 1 1 0 1 0 1 pd70f3 936 1 0 0 1 0 0 1 1 0 1 1 0 pd70f3 937 1 0 0 1 0 0 1 1 0 1 1 1 pd70f3 938 1 0 0 1 0 0 1 1 1 0 0 0 pd70f3 939 1 0 0 1 0 0 1 1 1 0 0 1 3.4.5 recommended use of address space the architecture of the v850e/sj3-h and v850e/sk3-h requir es that a register that se rves as a pointer be secured for address generation when operand data in the data spac e is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. because the number of gene ral-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose r egisters as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb spac e of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the program space, access the addresses 03ff0000h to 03ffefffh. caution if a branch instruction is at the upper limi t of the internal ram ar ea, a prefetch operation (invalid fetch) straddling the on-chip peripheral i/o area does not occur. chapter 3 cpu function user?s manual u19201ej3v0ud 101 (2) data space with the v850e/sj3-h and v850e/sk3-h, it seems that there are sixty-fo ur 64 mb address spaces on the 4 gb cpu address space. therefore, the least significant bi t (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st di sp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically eliminates the need for registers dedicated to pointers. example : pd70f3474 (v850e/sj3-h), 70f3475 (v8 50e/sj3-h), 70f3476 (v850e/sj3-h) internal rom area on-chip peripheral i/o area internal ram area 32 kb 4 kb 28 kb (r = ) 0013ffffh 00007fffh 00000000h fffff000h ffffefffh ffff8000h chapter 3 cpu function user?s manual u19201ej3v0ud 102 figure 3-14. recommended memory map (1/2) (a) when using expanded internal ram expanded internal ram data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03ff0000h 03feffffh 03fec000h 03febfffh 03fe4000h 03fe3fffh 02000000h 01ffffffh 00140000h 0013ffffh 00400000h 003fffffh 00000000h ffffffffh fffff000h ffffefffh ffff0000h fffeffffh fffec000h fffebfffh 00400000h 003fffffh 00000000h use prohibited use prohibited note fffe4000h fffe3fffh use prohibited expanded internal ram 03fff000h 03ffefffh note in the can controller version, the data space of addresses 03fec0 00h to 03feefffh is assigned as the programmable peripheral i/o area. only the prog rammable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map when the expanded internal ram of the pd70f3474 (v850e/sj3-h) is used (see 5.3.1 chip select control function ). chapter 3 cpu function user?s manual u19201ej3v0ud 103 figure 3-14. recommended memory map (2/2) (b) when not using expanded internal ram external memory data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03ff0000h 03feffffh 03fec000h 03febfffh 03e00000h 03dfffffh 02000000h 01ffffffh 00140000h 0013ffffh 00400000h 003fffffh 00000000h ffffffffh fffff000h ffffefffh ffff0000h fffeffffh fffec000h fffebfffh 00400000h 003fffffh 00000000h use prohibited use prohibited note ffe00000h ffdfffffh use prohibited external memory 03fff000h 03ffefffh note in the can controller version, the data space of addresses 03fec0 00h to 03feefffh is assigned as the programmable peripheral i/o area. only the prog rammable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map when the expanded internal ram of the pd70f3474 (v850e/sj3-h) is used (see 5.3.1 chip select control function ). chapter 3 cpu function user?s manual u19201ej3v0ud 104 3.4.6 peripheral i/o registers (1/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl register pdl 0000h note 1 fffff004h port dll register pdll 00h note 1 fffff005h port dlh register pdlh 00h note 1 fffff006h port dh register pdh 00h note 1 fffff008h port cs register pcs 00h note 1 fffff00ah port ct register pct 00h note 1 fffff00ch port cm register pcm 00h note 1 fffff00eh port cd register pcd 00h note 1 fffff024h port dl mode register pmdl ffffh fffff024h port dl mode register l pmdll ffh fffff025h port dl mode register h pmdlh ffh fffff026h port dh mode register pmdh ffh fffff028h port cs mode register pmcs ffh fffff02ah port ct mode register pmct ffh fffff02ch port cm mode register pmcm ffh fffff02eh port cd mode register pmcd ffh fffff044h port dl mode control register pmcdl 0000h fffff044h port dl mode control register l pmcdll 00h fffff045h port dl mode control register h pmcdlh 00h fffff046h port dh mode control register pmcdh 00h fffff048h port cs mode control register pmccs 00h fffff04ah port ct mode control register pmcct 00h fffff04ch port cm mode control register pmccm 00h fffff04eh port cd mode control register pmccd 00h fffff04fh port cd function control register pfccd 00h fffff060h chip area select control register 0 csc0 2c11h fffff062h chip area select control register 1 csc1 2c11h fffff064h peripheral i/o area select control register bpc note 2 0000h fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h r/w undefined notes 1. the value of the output latch is 00h or 0000h. the status of the pin is read during input. 2. can controller version only chapter 3 cpu function user?s manual u19201ej3v0ud 105 (2/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff108h interrupt mask register 4 imr4 ffffh fffff108h interrupt mask register 4l imr4l ffh fffff109h interrupt mask register 4h imr4h ffh fffff10ah interrupt mask register 5 imr5 ffffh fffff10ah interrupt mask register 5l imr5l ffh fffff10bh interrupt mask register 5h imr5h ffh fffff10ch interrupt mask register 6 imr6 ffffh fffff10ch interrupt mask register 6l imr6l ffh fffff10dh interrupt mask register 6h imr6h ffh fffff10eh interrupt mask register 7l imr7l 1fh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic0 r/w 47h chapter 3 cpu function user?s manual u19201ej3v0ud 106 (3/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 47h fffff128h interrupt control register tq0ccic2 47h fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 47h fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 47h fffff13eh interrupt control register tp3ovic 47h fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 47h fffff144h interrupt control register tp4ovic 47h fffff146h interrupt control register tp4ccic0 47h fffff148h interrupt control register tp4ccic1 47h fffff14ah interrupt control register tp5ovic 47h fffff14ch interrupt control register tp5ccic0 47h fffff14eh interrupt control register tp5ccic1 47h fffff150h interrupt control register tm0eqic0 47h fffff152h interrupt control register cb0ric/iicic1 47h fffff154h interrupt control register cb0tic 47h fffff156h interrupt control register cb1ric 47h fffff158h interrupt control register cb1tic 47h fffff15ah interrupt control register cb2ric 47h fffff15ch interrupt control register cb2tic 47h fffff15eh interrupt control register cb3ric 47h fffff160h interrupt control register cb3tic 47h fffff162h interrupt control register ua0ric/cb4ric 47h fffff164h interrupt control register ua0tic/cb4tic 47h fffff166h interrupt control register ua1ric r/w 47h chapter 3 cpu function user?s manual u19201ej3v0ud 107 (4/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff168h interrupt control register ua1tic 47h fffff16ah interrupt control register ua2ric 47h fffff16ch interrupt control register ua2tic 47h fffff16eh interrupt control register adic 47h fffff170h interrupt control register dmaic0 47h fffff172h interrupt control register dmaic1 47h fffff174h interrupt control register dmaic2 47h fffff176h interrupt control register dmaic3 47h fffff178h interrupt control register kric 47h fffff17ah interrupt control register wtiic 47h fffff17ch interrupt control register wtic 47h fffff17eh interrupt control register erric0 note 1 47h fffff180h interrupt control register wupic0 note 1 47h fffff182h interrupt control register recic0 note 1 47h fffff184h interrupt control register trxic0 note 1 47h fffff186h interrupt control register erric1 note 2 47h fffff188h interrupt control register wupic1 note 2 47h fffff18ah interrupt control register recic1 note 2 47h fffff18ch interrupt control register trxic1 note 2 47h fffff18eh interrupt control register pic8 47h fffff190h interrupt control register tp6ovic 47h fffff192h interrupt control register tp6ccic0 47h fffff194h interrupt control register tp6ccic1 47h fffff196h interrupt control register tp7ovic 47h fffff198h interrupt control register tp7ccic0 47h fffff19ah interrupt control register tp7ccic1 47h fffff19ch interrupt control register tp8ovic 47h fffff19eh interrupt control register tp8ccic0 47h fffff1a0h interrupt control register tp8ccic1 47h fffff1a2h interrupt control register cb5ric 47h fffff1a4h interrupt control register cb5tic 47h fffff1a6h interrupt control register ua3ric 47h fffff1a8h interrupt control register ua3tic 47h fffff1b0h interrupt control register ua4ric 47h fffff1b2h interrupt control register ua4tic 47h fffff1b4h interrupt control register iicic3 47h fffff1b6h interrupt control register iicic0 47h fffff1b8h interrupt control register iicic2 47h fffff1bah interrupt control register iicic4 note 3 47h fffff1bch interrupt control register iicic5 note 3 r/w 47h notes 1. can controller version only 2. can controller (2-channel) version only 3. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) chapter 3 cpu function user?s manual u19201ej3v0ud 108 (5/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff1beh interrupt control register pic9 47h fffff1c0h interrupt control register tp7iecic 47h fffff1c2h interrupt control register tp8iecic 47h fffff1c4h interrupt control register tm1eqic0 47h fffff1c6h interrupt control register tm2eqic0 47h fffff1c8h interrupt control register ce0tic note 47h fffff1cah interrupt control register ce0tiofic note 47h fffff1cch interrupt control register ce1tic note 47h fffff1ceh interrupt control register ce1tiofic note 47h fffff1d0h interrupt control register ub0tiric 47h fffff1d2h interrupt control register ub0titic 47h fffff1d4h interrupt control register ub0tific 47h fffff1d6h interrupt control register ub0tireic 47h fffff1d8h interrupt control register ub0titoic 47h fffff1dah interrupt control register ub1tiric 47h fffff1dch interrupt control register ub1titic 47h fffff1deh interrupt control register ub1tific 47h fffff1e0h interrupt control register ub1tireic 47h fffff1e2h interrupt control register ub1titoic 47h fffff1e4h interrupt control register ua5ric 47h fffff1e6h interrupt control register ua5tic 47h fffff1e8h interrupt control register erric 47h fffff1eah interrupt control register staic 47h fffff1ech interrupt control register ieic1 47h fffff1eeh interrupt control register ieic2 47h fffff1f0h interrupt control register rtc0ic 47h fffff1f2h interrupt control register rtc1ic 47h fffff1f4h interrupt control register rtc2ic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail compare mode register ada0pfm 00h fffff205h power-fail compare threshold value register ada0pft r/w 00h fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0cr0h undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0cr1h r undefined note not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) chapter 3 cpu function user?s manual u19201ej3v0ud 109 (6/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0cr2h undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0cr3h undefined fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0cr4h undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0cr5h undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0cr6h undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0cr7h undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0cr8h undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0cr9h undefined fffff224h a/d conversion result register 10 ada0cr10 undefined fffff225h a/d conversion result register 10h ada0cr10h undefined fffff226h a/d conversion result register 11 ada0cr11 undefined fffff227h a/d conversion result register 11h ada0cr11h undefined fffff228h a/d conversion result register 12 ada0cr12 undefined fffff229h a/d conversion result register 12h ada0cr12h undefined fffff22ah a/d conversion result register 13 ada0cr13 undefined fffff22bh a/d conversion result register 13h ada0cr13h undefined fffff22ch a/d conversion result register 14 ada0cr14 undefined fffff22dh a/d conversion result register 14h ada0cr14h undefined fffff22eh a/d conversion result register 15 ada0cr15 undefined fffff22fh a/d conversion result register 15h ada0cr15h r undefined fffff280h d/a converter conversion va lue setting register 0 da0cs0 00h fffff281h d/a converter conversion va lue setting register 1 da0cs1 00h fffff282h d/a converter mode register da0m 00h fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff310h crc input register crcin 00h fffff312h crc data register crcd 0000h fffff318h noise elimination control register nfc 00h fffff31ch tmp7 noise elimination control register en0nfc 00h fffff31eh tmp8 noise elimination control register en1nfc 00h fffff320h brg1 prescaler mode register prsm1 00h fffff321h brg1 prescaler compare register prscm1 00h fffff324h brg2 prescaler mode register prsm2 00h fffff325h brg2 prescaler compare register prscm2 r/w 00h chapter 3 cpu function user?s manual u19201ej3v0ud 110 (7/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff328h brg3 prescaler mode register prsm3 00h fffff329h brg3 prescaler compare register prscm3 00h fffff340h iic division clock select register 0 ocks0 00h fffff344h iic division clock select register 1 ocks1 00h fffff348h iebus clock select register ocks2 00h fffff34ch iic division clock select register 3 ocks3 note 1 00h fffff360h iebus control register bcr 00h fffff361h iebus power save register psr r/w 00h fffff362h iebus slave status register ssr 81h fffff363h iebus unit status register usr r 00h fffff364h iebus interrupt status register isr 00h fffff365h iebus error status register esr 00h fffff366h iebus unit address register uar 0000h fffff368h iebus slave address register sar r/w 0000h fffff36ah iebus partner ad dress register par 0000h fffff36ch iebus receive slave address register rsa r 0000h fffff36eh iebus control data register cdr 00h fffff36fh iebus telegraph length register dlr 01h fffff370h iebus data register dr r/w 00h fffff371h iebus field status register fsr 00h fffff372h iebus success count register scr 01h fffff373h iebus communication count register ccr r 20h fffff3f0h sscg control register sscgctl 00h fffff3f1h sscg frequency control register 0 sfc0 00h fffff3f2h sscg frequency control register 1 sfc1 00h fffff400h port 0 register p0 00h note 2 fffff402h port 1 register p1 00h note 2 fffff404h port 2 register p2 00h note 2 fffff406h port 3 register p3 0000h note 2 fffff406h port 3l register p3l 00h note 2 fffff407h port 3h register p3h 00h note 2 fffff408h port 4 register p4 00h note 2 fffff40ah port 5 register p5 00h note 2 fffff40ch port 6 register p6 0000h note 2 fffff40ch port 6l register p6l 00h note 2 fffff40dh port 6h register p6h 00h note 2 fffff40eh port 7l register p7l 00h note 2 fffff40fh port 7h register p7h 00h note 2 fffff410h port 8 register p8 r/w 00h note 2 notes 1. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) 2. the value of the output latch is 00h or 0000h. the status of the pin is read during input. chapter 3 cpu function user?s manual u19201ej3v0ud 111 (8/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff412h port 9 register p9 0000h note 1 fffff412h port 9l register p9l 00h note 1 fffff413h port 9h register p9h 00h note 1 fffff41ah port 13 register p13 note 2 00h note 1 fffff41ch port 14 register p14 note 2 00h note 1 fffff41eh port 15 register p15 note 2 00h note 1 fffff420h port 0 mode register pm0 ffh fffff422h port 1 mode register pm1 ffh fffff424h port 2 mode register pm2 note ffh fffff426h port 3 mode register pm3 ffffh fffff426h port 3 mode register l pm3l ffh fffff427h port 3 mode register h pm3h ffh fffff428h port 4 mode register pm4 ffh fffff42ah port 5 mode register pm5 ffh fffff42ch port 6 mode register pm6 ffffh fffff42ch port 6 mode register l pm6l ffh fffff42dh port 6 mode register h pm6h ffh fffff42eh port 7 mode register l pm7l ffh fffff42fh port 7 mode register h pm7h ffh fffff430h port 8 mode register pm8 ffh fffff432h port 9 mode register pm9 ffffh fffff432h port 9 mode register l pm9l ffh fffff433h port 9 mode register h pm9h ffh fffff43ah port 13 mode register pm13 note 2 ffh fffff43ch port 14 mode register pm14 note 2 ffh fffff43eh port 15 mode register pm15 note 2 ffh fffff440h port 0 mode control register pmc0 00h fffff444h port 2 mode control register pmc2 note 2 00h fffff446h port 3 mode control register pmc3 0000h fffff446h port 3 mode control register l pmc3l 00h fffff447h port 3 mode control register h pmc3h 00h fffff448h port 4 mode control register pmc4 00h fffff44ah port 5 mode control register pmc5 00h fffff44ch port 6 mode control register pmc6 0000h fffff44ch port 6 mode control register l pmc6l 00h fffff44dh port 6 mode control register h pmc6h 00h fffff450h port 8 mode control register pmc8 00h fffff452h port 9 mode control register pmc9 0000h fffff452h port 9 mode control register l pmc9l 00h fffff453h port 9 mode control register h pmc9h r/w 00h notes 1. the value of the output latch is 00h or 0000h. the status of the pin is read during input. 2. v850e/sk3-h only chapter 3 cpu function user?s manual u19201ej3v0ud 112 (9/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff45eh port 15 mode control register pmc15 note 00h fffff460h port 0 function control register pfc0 00h fffff466h port 3 function control register pfc3 0000h fffff466h port 3 function control register l pfc3l 00h fffff467h port 3 function control register h pfc3h 00h fffff468h port 4 function control register pfc4 00h fffff46ah port 5 function control register pfc5 00h fffff46ch port 6 function control register pfc6 0000h fffff46ch port 6 function control register l pfc6l 00h fffff46dh port 6 function control register h pfc6h 00h fffff470h port 8 function control register pfc8 00h fffff472h port 9 function control register pfc9 0000h fffff472h port 9 function control register l pfc9l 00h fffff473h port 9 function control register h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff486h data wait control register 1 dwc1 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 00h fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 r/w 00h note v850e/sk3-h only chapter 3 cpu function user?s manual u19201ej3v0ud 113 (10/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 r/w 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff5d0h tmp4 control register 0 tp4ctl0 00h fffff5d1h tmp4 control register 1 tp4ctl1 00h fffff5d2h tmp4 i/o control register 0 tp4ioc0 00h fffff5d3h tmp4 i/o control register 1 tp4ioc1 00h fffff5d4h tmp4 i/o control register 2 tp4ioc2 00h fffff5d5h tmp4 option register 0 tp4opt0 00h fffff5d6h tmp4 capture/compare register 0 tp4ccr0 0000h fffff5d8h tmp4 capture/compare register 1 tp4ccr1 r/w 0000h fffff5dah tmp4 counter read buffer register tp4cnt r 0000h fffff5e0h tmp5 control register 0 tp5ctl0 00h fffff5e1h tmp5 control register 1 tp5ctl1 00h fffff5e2h tmp5 i/o control register 0 tp5ioc0 00h fffff5e3h tmp5 i/o control register 1 tp5ioc1 00h fffff5e4h tmp5 i/o control register 2 tp5ioc2 00h fffff5e5h tmp5 option register 0 tp5opt0 00h fffff5e6h tmp5 capture/compare register 0 tp5ccr0 r/w 0000h fffff5e8h tmp5 capture/compare register 1 tp5ccr1 r/w 0000h fffff5eah tmp5 counter read buffer register tp5cnt r 0000h chapter 3 cpu function user?s manual u19201ej3v0ud 114 (11/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5f0h tmp6 control register 0 tp6ctl0 00h fffff5f1h tmp6 control register 1 tp6ctl1 00h fffff5f2h tmp6 i/o control register 0 tp6ioc0 00h fffff5f3h tmp6 i/o control register 1 tp6ioc1 00h fffff5f4h tmp6 i/o control register 2 tp6ioc2 00h fffff5f5h tmp6 option register 0 tp6opt0 00h fffff5f6h tmp6 capture/compare register 0 tp6ccr0 0000h fffff5f8h tmp6 capture/compare register 1 tp6ccr1 r/w 0000h fffff5fah tmp6 counter read buffer register tp6cnt r 0000h fffff640h tmp7 control register 0 tp7ctl0 00h fffff641h tmp7 control register 1 tp7ctl1 00h fffff642h tmp7 control register 2 tp7ctl2 00h fffff643h tmp7 i/o control register 0 tp7ioc0 00h fffff644h tmp7 i/o control register 1 tp7ioc1 00h fffff645h tmp7 i/o control register 2 tp7ioc2 00h fffff646h tmp7 i/o control register 3 tp7ioc3 00h fffff647h tmp7 option register 0 tp7opt0 00h fffff648h tmp7 option register 1 tp7opt1 00h fffff64ah tmp7 capture/compare register 0 tp7ccr0 0000h fffff64ch tmp7 capture/compare register 1 tp7ccr1 r/w 0000h fffff64eh tmp7 counter read buffer register tp7cnt r 0000h fffff650h tmp7 counter write register tp7tcw 0000h fffff660h tmp8 control register 0 tp8ctl0 00h fffff661h tmp8 control register 1 tp8ctl1 00h fffff662h tmp8 control register 2 tp8ctl2 00h fffff663h tmp8 i/o control register 0 tp8ioc0 00h fffff664h tmp8 i/o control register 1 tp8ioc1 00h fffff665h tmp8 i/o control register 2 tp8ioc2 00h fffff666h tmp8 i/o control register 3 tp8ioc3 00h fffff667h tmp8 option register 0 tp8opt0 00h fffff668h tmp8 option register 1 tp8opt1 00h fffff66ah tmp8 capture/compare register 0 tp8ccr0 0000h fffff66ch tmp8 capture/compare register 1 tp8ccr1 r/w 0000h fffff66eh tmp8 counter read buffer register tp8cnt r 0000h fffff670h tmp8 counter write register tp8tcw 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6a0h tmm1 control register 0 tm1ctl0 00h fffff6a4h tmm1 compare register 0 tm1cmp0 0000h fffff6b0h tmm2 control register 0 tm2ctl0 00h fffff6b4h tmm2 compare register 0 tm2cmp0 r/w 0000h chapter 3 cpu function user?s manual u19201ej3v0ud 115 (12/19) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff6e0h real-time output buffer register 0l rtbl0 00h fffff6e2h real-time output buffer register 0h rtbh0 00h fffff6e4h real-time output port mode register 0 rtpm0 00h fffff6e5h real-time output port control register 0 rtpc0 00h fffff6f0h real-time output buffer register 1l rtbl1 00h fffff6f2h real-time output buffer register 1h rtbh1 00h fffff6f4h real-time output port mode register 1 rtpm1 00h fffff6f5h real-time output port control register 1 rtpc1 00h fffff700h port 0 function control expansion register pfce0 note 00h fffff706h port 3 function control expansion register pfce3 0000h fffff706h port 3 function control expansion register l pfce3l 00h fffff707h port 3 function control expansion register h pfce3h 00h fffff70ah port 5 function control expansion register pfce5 00h fffff70ch port 6 function control expansion register pfce6 0000h fffff70ch port 6 function control expansion register l pfce6l 00h fffff70dh port 6 function control expansion register h pfce6h 00h fffff710h port 8 function control expansion register pfce8 00h fffff712h port 9 function control expansion register pfce9 0000h fffff712h port 9 function control expansion register l pfce9l 00h fffff713h port 9 function control expansion register h pfce9h 00h fffff802h system status register sys 00h fffff80ch internal oscillation mode register rcm 00h fffff810h dma trigger factor register 0 dtfr0 00h fffff812h dma trigger factor register 1 dtfr1 00h fffff814h dma trigger factor register 2 dtfr2 00h fffff816h dma trigger factor register 3 dtfr3 00h fffff820h power save mode register psmr 00h fffff822h clock control register ckc r/w 0ah fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operation clock status register ccls r 00h fffff840h correction address register 0 corad0 00000000h fffff840h correction address register 0l corad0l 0000h fffff842h correction address register 0h corad0h 0000h fffff844h correction address register 1 corad1 00000000h fffff844h correction address register 1l corad1l 0000h fffff846h correction address register 1h corad1h r/w 0000h note not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) chapter 3 cpu function user?s manual u19201ej3v0ud 116 (13/19) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff848h correction address register 2 corad2 00000000h fffff848h correction address register 2l corad2l 0000h fffff84ah correction address register 2h corad2h 0000h fffff84ch correction address register 3 corad3 00000000h fffff84ch correction address register 3l corad3l 0000h fffff84eh correction address register 3h corad3h 0000h fffff850h correction address register 4 corad4 00000000h fffff850h correction address register 4l corad4l 0000h fffff852h correction address register 4h corad4h 0000h fffff854h correction address register 5 corad5 00000000h fffff854h correction address register 5l corad5l 0000h fffff856h correction address register 5h corad5h 0000h fffff858h correction address register 6 corad6 00000000h fffff858h correction address register 6l corad6l 0000h fffff85ah correction address register 6h corad6h 0000h fffff85ch correction address register 7 corad7 00000000h fffff85ch correction address register 7l corad7l 0000h fffff85eh correction address register 7h corad7h 0000h fffff870h clock monitor mode register clm 00h fffff880h correction control register corcn 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams 01h note 1 fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff900h csie0 control register 0 ce0ctl0 note 2 00h fffff901h csie0 control register 1 ce0ctl1 note 2 r/w 07h fffff902h csie0 receive data buffer register ce0rx0 note 2 0000h fffff902h csie0 receive data buffer register l ce0rx0l note 2 00h fffff903h csie0 receive data buffer register h ce0rx0h note 2 r 00h fffff906h csie0 transmit data buffer register ce0tx0 note 2 0000h fffff906h csie0 transmit data buffer register l ce0tx0l note 2 00h fffff907h csie0 transmit data buffer register h ce0tx0h note 2 00h fffff908h csie0 status register ce0str note 2 20h fffff909h csie0 control register 2 ce0ctl2 note 2 00h fffff90ch csie0 control register 3 ce0ctl3 note 2 00h fffff940h csie1 control register 0 ce1ctl0 note 2 00h fffff941h csie1 control register 1 ce1ctl1 note 2 r/w 07h notes 1. the default value indicates the value after the power is turned on. the status before a reset is retained after the reset. 2. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) chapter 3 cpu function user?s manual u19201ej3v0ud 117 (14/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff942h csie1 receive data buffer register ce1rx0 note 1 0000h fffff942h csie1 receive data buffer register l ce1rx0l note 1 00h fffff943h csie1 receive data buffer register h ce1rx0h note 1 00h fffff946h csie1 transmit data buffer register ce1tx0 note 1 0000h fffff946h csie1 transmit data buffer register l ce1tx0l note 1 00h fffff947h csie1 transmit data buffer register h ce1tx0h note 1 00h fffff948h csie1 status register ce1str note 1 20h fffff949h csie1 control register 2 ce1ctl2 note 1 00h fffff94ch csie1 control register 3 ce1ctl3 note 1 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emul ation register 1 pemu1 note 2 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 transmit data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx ffh fffffa30h uarta3 control register 0 ua3ctl0 10h fffffa31h uarta3 control register 1 ua3ctl1 00h fffffa32h uarta3 control register 2 ua3ctl2 r/w ffh fffffa33h uarta3 option control register 0 ua3opt0 14h fffffa34h uarta3 status register ua3str r/w 00h fffffa36h uarta3 receive data register ua3rx r ffh fffffa37h uarta3 transmit data register ua3tx ffh fffffa40h uarta4 control register 0 ua4ctl0 r/w 10h notes 1. not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) 2. only during emulation chapter 3 cpu function user?s manual u19201ej3v0ud 118 (15/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffa41h uarta4 control register 1 ua4ctl1 00h fffffa42h uarta4 control register 2 ua4ctl2 ffh fffffa43h uarta4 option control register 0 ua4opt0 14h fffffa44h uarta4 status register ua4str r/w 00h fffffa46h uarta4 receive data register ua4rx r ffh fffffa47h uarta4 transmit data register ua4tx ffh fffffa50h uarta5 control register 0 ua5ctl0 10h fffffa51h uarta5 control register 1 ua5ctl1 00h fffffa52h uarta5 control register 2 ua5ctl2 ffh fffffa53h uarta5 option control register 0 ua5opt0 14h fffffa54h uarta5 status register ua5str r/w 00h fffffa56h uarta5 receive data register ua5rx r ffh fffffa57h uarta5 transmit data register ua5tx ffh fffffa80h uartb0 control register 0 ub0ctl0 10h fffffa82h uartb0 control register 2 ub0ctl2 ffffh fffffa84h uartb0 status register ub0str r/w 00h fffffa86h uartb0 receive data register ap ub0rxap 00ffh fffffa86h uartb0 receive data register ub0rx r ffh fffffa88h uartb0 transmit data register ub0tx w ffh fffffa8ah uartb0 fifo control register 0 ub0fic0 00h fffffa8bh uartb0 fifo control register 1 ub0fic1 00h fffffa8ch uartb0 fifo control register 2 ub0fic2 0000h fffffa8ch uartb0 fifo control register 2l ub0fic2l 00h fffffa8dh uartb0 fifo control register 2h ub0fic2h r/w 00h fffffa8eh uartb0 fifo status register 0 ub0fis0 00h fffffa8fh uartb0 fifo status register 1 ub0fis1 r 10h fffffaa0h uartb1 control register 0 ub1ctl0 10h fffffaa2h uartb1 control register 2 ub1ctl2 ffffh fffffaa4h uartb1 status register ub1str r/w 00h fffffaa6h uartb1 receive data register ap ub1rxap 00ffh fffffaa6h uartb1 receive data register ub1rx r ffh fffffaa8h uartb1 transmit data register ub1tx w ffh fffffaaah uartb1 fifo control register 0 ub1fic0 00h fffffaabh uartb1 fifo control register 1 ub1fic1 00h fffffaach uartb1 fifo control register 2 ub1fic2 0000h fffffaach uartb1 fifo control register 2l ub1fic2l 00h fffffaadh uartb1 fifo control register 2h ub1fic2h r/w 00h fffffaaeh uartb1 fifo status register 0 ub1fis0 00h fffffaafh uartb1 fifo status register 1 ub1fis1 10h fffffad0h subcount register rc1subc r 0000h fffffad2h second count register rc1sec 00h fffffad3h minute count register rc1min r/w 00h chapter 3 cpu function user?s manual u19201ej3v0ud 119 (16/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffad4h hour count register rc1hour 12h fffffad5h week count register rc1week 00h fffffad6h day count register rc1day 01h fffffad7h month count register rc1month 01h fffffad8h year count register rc1year 00h fffffad9h watch error correct register rc1subu 00h fffffadah alarm minute setting register rc1alm 00h fffffadbh alarm hour setting register rc1alh 12h fffffadch alarm week setting register rc1alw 00h fffffaddh real-time counter control register 0 rc1cc0 00h fffffadeh real-time counter control register 1 rc1cc1 00h fffffadfh real-time counter control register 2 rc1cc2 00h fffffae0h real-time counter control register 3 rc1cc3 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc06h external interrupt falling edge specification register 3 intf3 00h fffffc08h external interrupt falling edge specification register 4 intf4 00h fffffc0ah external interrupt falling edge specification register 5 intf5 00h fffffc0ch external interrupt falling edge specification register 6 intf6 00h fffffc10h external interrupt falling edge specification register 8 intf8 00h fffffc12h external interrupt falling edge specification register 9 intf9 0000h fffffc12h external interrupt falling edge specification register 9l intf9l 00h fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc1eh external interrupt falling edge specification register 15 intf15 note 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc26h external interrupt rising edge specification register 3 intr3 00h fffffc28h external interrupt rising edge specification register 4 intr4 00h fffffc2ah external interrupt rising edge specification register 5 intr5 00h fffffc2ch external interrupt rising edge specification register 6 intr6 00h fffffc30h external interrupt rising edge specification register 8 intr8 00h fffffc32h external interrupt rising edge specification register 9 intr9 0000h fffffc32h external interrupt rising edge specification register 9l intr9l 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc3eh external interrupt rising edge specification register 15 intr15 note 00h fffffc60h port 0 function register pf0 00h fffffc64h port 2 function register pf2 note 00h fffffc66h port 3 function register pf3 0000h fffffc66h port 3 function register l pf3l 00h fffffc67h port 3 function register h pf3h 00h fffffc68h port 4 function register pf4 00h fffffc6ah port 5 function register pf5 r/w 00h note v850e/sk3-h only chapter 3 cpu function user?s manual u19201ej3v0ud 120 (17/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc6ch port 6 function register pf6 0000h fffffc6ch port 6 function register l pf6l 00h fffffc6dh port 6 function register h pf6h 00h fffffc70h port 8 function register pf8 00h fffffc72h port 9 function register pf9 0000h fffffc72h port 9 function register l pf9l 00h fffffc73h port 9 function register h pf9h 00h fffffc7eh port 15 function register pf15 note r/w 00h fffffcc8h product selection register l prdsell depends on product fffffccah product selection register h prdselh r depends on product fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1 control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 01h fffffd21h csib2 control register 1 cb2ctl1 00h fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r 00h fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl 00h fffffd30h csib3 control register 0 cb3ctl0 01h fffffd31h csib3 control register 1 cb3ctl1 00h fffffd32h csib3 control register 2 cb3ctl2 00h fffffd33h csib3 status register cb3str r/w 00h fffffd34h csib3 receive data register cb3rx 0000h fffffd34h csib3 receive data register l cb3rxl r 00h note v850e/sk3-h only chapter 3 cpu function user?s manual u19201ej3v0ud 121 (18/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffd36h csib3 transmit data register cb3tx 0000h fffffd36h csib3 transmit data register l cb3txl 00h fffffd40h csib4 control register 0 cb4ctl0 01h fffffd41h csib4 control register 1 cb4ctl1 00h fffffd42h csib4 control register 2 cb4ctl2 00h fffffd43h csib4 status register cb4str r/w 00h fffffd44h csib4 receive data register cb4rx 0000h fffffd44h csib4 receive data register l cb4rxl r 00h fffffd46h csib4 transmit data register cb4tx 0000h fffffd46h csib4 transmit data register l cb4txl 00h fffffd50h csib5 control register 0 cb5ctl0 01h fffffd51h csib5 control register 1 cb5ctl1 00h fffffd52h csib5 control register 2 cb5ctl2 00h fffffd53h csib5 status register cb5str r/w 00h fffffd54h csib5 receive data register cb5rx 0000h fffffd54h csib5 receive data register l cb5rxl r 00h fffffd56h csib5 transmit data register cb5tx 0000h fffffd56h csib5 transmit data register l cb5txl 00h fffffd80h iic shift register 0 iic0 00h fffffd82h iic control register 0 iicc0 00h fffffd83h slave address register 0 sva0 00h fffffd84h iic clock select register 0 iiccl0 00h fffffd85h iic function expansion register 0 iicx0 r/w 00h fffffd86h iic status register 0 iics0 r 00h fffffd8ah iic flag register 0 iicf0 00h fffffd90h iic shift register 1 iic1 00h fffffd92h iic control register 1 iicc1 00h fffffd93h slave address register 1 sva1 00h fffffd94h iic clock select register 1 iiccl1 00h fffffd95h iic function expansion register 1 iicx1 r/w 00h fffffd96h iic status register 1 iics1 r 00h fffffd9ah iic flag register 1 iicf1 00h fffffda0h iic shift register 2 iic2 00h fffffda2h iic control register 2 iicc2 00h fffffda3h slave address register 2 sva2 00h fffffda4h iic clock select register 2 iiccl2 00h fffffda5h iic function expansion register 2 iicx2 r/w 00h fffffda6h iic status register 2 iics2 r 00h fffffdaah iic flag register 2 iicf2 00h fffffdb0h iic shift register 3 iic3 00h fffffdb2h iic control register 3 iicc3 00h fffffdb3h slave address register 3 sva3 r/w 00h chapter 3 cpu function user?s manual u19201ej3v0ud 122 (19/19) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffdb4h iic clock select register 3 iiccl3 00h fffffdb5h iic function expansion register 3 iicx3 r/w 00h fffffdb6h iic status register 3 iics3 r 00h fffffdbah iic flag register 3 iicf3 00h fffffdc0h iic shift register 4 iic4 note 00h fffffdc2h iic control register 4 iicc4 note 00h fffffdc3h slave address register 4 sva4 note 00h fffffdc4h iic clock select register 4 iiccl4 note 00h fffffdc5h iic function expansion register 4 iicx4 note r/w 00h fffffdc6h iic status register 4 iics4 note r 00h fffffdcah iic flag register 4 iicf4 note 00h fffffdd0h iic shift register 5 iic5 note 00h fffffdd2h iic control register 5 iicc5 note 00h fffffdd3h slave address register 5 sva5 note 00h fffffdd4h iic clock select register 5 iiccl5 note 00h fffffdd5h iic function expansion register 5 iicx5 note r/w 00h fffffdd6h iic status register 5 iics5 note r 00h fffffddah iic flag register 5 iicf5 note 00h ffffffbeh external bus interface mode control register eximc r/w 00h note not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) chapter 3 cpu function user?s manual u19201ej3v0ud 123 3.4.7 programmable peripheral i/o registers the bpc register is used for programmable peripheral i/o register area selection. (1) peripheral i/o area selec t control register (bpc) the bpc register can be read or written in 16-bit units. reset sets this register to 0000h. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address default value bpc pa15 0 pa13 pa12 pa11 pa10 pa09 pa08 pa07 pa06 pa05 pa04 pa03 pa02 pa01 pa00 fffff064h 0000h bit position bit name function enables/disables usage of prog rammable peripheral i/o area. pa15 usage of programmable peripheral i/o area 0 usage of programmable peripheral i/o area disabled 1 usage of programmable peripheral i/o area enabled 15 pa15 13 to 0 pa13 to pa00 specify an address in programmabl e peripheral i/o area (corresponding to a27 to a14, respectively). caution when setting the pa15 bit to 1, be sure to set the bpc register to 8ffbh. when clearing the pa15 bit to 0, be su re to set the bpc register to 0000h. for a list of the programmable peripheral i/o register areas, see table 21-16 register access types . chapter 3 cpu function user?s manual u19201ej3v0ud 124 3.4.8 special registers special registers are registers that are protected from being written with illegal data due to a program hang-up. the v850e/sj3-h and v850e/sk3-h have the following ten special registers. ? power save control register (psc) ? clock control register (ckc) ? processor clock control register (pcc) ? sscg frequency control register 0 (sfc0) ? sscg frequency control register 1 (sfc1) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) ? internal ram data status register (rams) ? on-chip debug mode register (ocdm) in addition, the prcdm register is provided to protect again st a write access to the spec ial registers so that the application system does not inadv ertently stop due to a program hang-up. a write access to the special registers is made in a specific sequence, and an illegal st ore operation is reported to the sys register. chapter 3 cpu function user?s manual u19201ej3v0ud 125 (1) setting data to special registers set data to the special registers in the following sequence. <1> disable dma operation. <2> prepare data to be set to the special register in a general-purpose register. <3> write the data prepared in <2> to the prcmd register. <4> write the setting data to the special re gister (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) (<5> to <9> insert nop instructions (5 instructions).) note <10> enable dma operation if necessary. [example] with psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle1, idle2, and stop modes). <1>clr1 0, dchcn[r0] ; disable dma operation. n = 0 to 3 <2>mov0x02, r10 <3>st.b r10, prcmd[r0] ; write prcmd register. <4>st.b r10, psc[r0] ; set psc register. <5>nop note ; dummy instruction <6>nop note ; dummy instruction <7>nop note ; dummy instruction <8>nop note ; dummy instruction <9>nop note ; dummy instruction <10>set1 0, dchcn[r0] ; enable dma operation. n = 0 to 3 (next instruction) there is no special sequence to read a special register. note five nop instructions or more must be inserted immediately after setting the idle1 mode, idle2 mode, or stop mode (by setting the psc.stp bit to 1). cautions 1. when a store instruction is executed to store data in the comma nd register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e prcmd register, use the same general-purpose register used to set the speci al register (<4> in example) to write data to the prcmd register (<3> in example). the same applies when a general-purpose register is used for addressing. chapter 3 cpu function user?s manual u19201ej3v0ud 126 (2) command register (prcmd) the prcmd register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that t he system does not inadvertently stop due to a program hang-up. the first write access to a special register is valid after data has be en written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific se quence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). reset makes this register undefined. 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch chapter 3 cpu function user?s manual u19201ej3v0ud 127 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 protection error did not occur protection error occurred prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <4> is executed without executing <3> in 3.4.8 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o register other than a special register (including execution of a bit manipulation instruction) afte r writing data to the prcmd register (if <4> in 3.4.8 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is read (except by a bit manipulation instruction) between an operation to write the prcmd register and an operation to write a special register, the prerr flag is not set, and the set dat a can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcm d register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd regist er, which is not a special register, immediately after a write access to the prcmd regi ster, the prerr bit is set to 1. chapter 3 cpu function user?s manual u19201ej3v0ud 128 3.4.9 cautions (1) registers to be set first be sure to set the following registers first when using the v850e/sj3-h and v850e/sk3-h. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register 2 (wdtm2) ? registers related to expanded internal ram ? bus size configuration register (bsc) ? data wait control register 1 (dwc1) ? address wait control register (awc) ? bus cycle control register (bcc) ? program id register (asid) ? initialization setting registers w hen using clock modes 2, 3, and 4 ? clock control register (ckc) ? sscg frequency control register 0 (sfc0) ? sscg frequency control register 1 (sfc1) after setting the above registers, set the other registers as necessary. when using the external bus, set each pin to the alternate-function bus control pin mode by using the port- related registers after setting the above registers. (a) system wait control register (vswc) the vswc register controls wait of bus a ccess to the on-chip peripheral i/o registers. three clocks are required to access an on-chip pe ripheral i/o register (without a wait cycle). the v850e/sj3-h and v850e/sk3-h require wait cycles according to the operating frequency. set the following value to the vswc register in accordance with the frequency used. the vswc register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc number of waits 32 khz f clk < 16.6 mhz 00h 0 (no waits) 16.6 mhz f clk < 25 mhz 01h 1 25 mhz f clk < 33.3 mhz 11h 2 33.3 mhz f clk 48 mhz 12h 3 (b) on-chip debug mode register (ocdm) for details, see chapter 34 on-chip debug function . (c) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and the operation clock of the watchdog timer 2. the watchdog timer 2 automatically st arts in the reset mode after reset is released. write the wdtm2 register to activate this operation. for details, refer to chapter 11 functions of watchdog timer 2 . chapter 3 cpu function user?s manual u19201ej3v0ud 129 (d) registers related to expanded internal ram the expanded internal ram is accessed via the external bus interface. before accessing the expanded internal ram, be sure to set the registers related to the external bus interface (initial settings for the expanded internal ram). for details, refer to 3.4.4 (6) expanded internal ram . (e) program id register (asid) for details, refer to 3.2.2 (8) program id register (asid) . (f) initialization setting register wh en using clock modes 2, 3, and 4 for details, refer to 6.4.4 (1) initialization setting for using clock modes 2, 3, and 4 . (2) accessing specific on-chip peripheral i/o registers this product has two types of internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with low-speed peripheral hardware. the clock of the cpu bus and the clock of the peripher al bus are asynchronous. if an access to the cpu and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. if there is a possibility of a conflict, the number of cycles for acce ssing the cpu changes when t he peripheral hardware is accessed, so that correct data is transferred. as a result, the cpu does not start processing of the next instruction but enters the wait state. if this wait st ate occurs, the number of clocks required to execute an instruction increases by the number of wait clocks shown below. this must be taken into consideration if real-time processing is required. when specific on-chip peripheral i/o registers are access ed, more wait states may be required in addition to the wait states set by the vswc register. the access conditions and how to calculate the number of wait states to be inserted (number of cpu clocks) at this time are shown below. chapter 3 cpu function user?s manual u19201ej3v0ud 130 (1/2) peripheral function register name access k tpncnt read 1 or 2 write ? 1st access: no wait ? continuous write: 0 to 3 16-bit timer/event counter p (tmp) (n = 0 to 8) tpnccr0, tpnccr1 read 1 or 2 tq0cnt read 1 or 2 write ? 1st access: no wait ? continuous write: 0 to 3 16-bit timer/event counter q (tmq) tq0ccr0 to tq0ccr3 read 1 or 2 cenctl0 note write 1 to 5 centx0 note write 0 to 4 3-wire variable-length serial i/o e (csie) note (n = 0, 1) censtr note read 1 to 5 ubntx write 0 to 4 asynchronous serial interface b (uartb) (n = 0, 1) ubnrx ubnrxap ubnfis0 ubnfis1 read 1 to 5 watchdog timer 2 (wdt2) wdtm2 write (when wdt2 operating) 3 rtbl0, rtbl1 write (rtpcn.rtpoen bit = 0) 1 real-time output function (rto) rtbh0, rtbh1 write (rtpcn.rtpoen bit = 0) 1 ada0m0 read 1 to 3 ada0cr0 to ada0cr15 read 1 to 3 a/d converter ada0cr0h to ada0cr15h read 1 to 3 i 2 c00 to i 2 c03, i 2 c04 note , i 2 c05 note iics0 to iics3, iics4 note , iics5 note read 1 note not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) chapter 3 cpu function user?s manual u19201ej3v0ud 131 (2/2) peripheral function register name access k cngmabt note 1 , cngmabtd note 1 , cnmaskal note 1 , cnmaskah note 1 , cnlec note 1 , cninfo note 1 , cnerc note 1 , cnie note 1 , cnints note 1 , cnbrp note 1 , cnbtr note 1 , cnts note 1 read/write (f cpu /f canmod + 1)/(2 + j) (min.) note 2 (2 f cpu /f canmod + 1)/(2 + j) (max.) note 2 cngmctrl note 1 , cngmcs note 1 , cnctrl note 1 read/write (f cpu /f can + 1)/(2 + j) (min.) note 2 (2 f cpu /f can + 1)/(2 + j) (max.) note 2 write (f cpu /f canmod + 1)/(2 + j) (min.) note 2 (2 f cpu /f canmod + 1)/(2 + j) (max.) note 2 cnrgpt note 1 , cntgpt note 1 read (3 f cpu /f canmod + 1)/(2 + j) (min.) note 2 (4 f cpu /f canmod + 1)/(2 + j) (max.) note 2 cnlipt note 1 , cnlopt note 1 read (3 f cpu /f canmod + 1)/(2 + j) (min.) note 2 (4 f cpu /f canmod + 1)/(2 + j) (max.) note 2 write (4 f cpu /f can + 1)/(2 + j) (min.) note 2 (5 f cpu /f can + 1)/(2 + j) (max.) note 2 cnmctrlm note 1 read (3 f cpu /f can + 1)/(2 + j) (min.) note 2 (4 f cpu /f can + 1)/(2 + j) (max.) note 2 write (8 bits) (4 f cpu /f canmod + 1)/(2 + j) (min.) note 2 (5 f cpu /f canmod + 1)/(2 + j) (max.) note 2 write (16 bits) (2 f cpu /f canmod + 1)/(2 + j) (min.) note (3 f cpu /f canmod + 1)/(2 + j) (max.) note can controller note 1 (n = 0, 1, m = 0 to 31, a = 1 to 4) cnmdata01m note 1 , cnmdata0m note 1 , cnmdata1m note 1 , cnmdata23m note 1 , cnmdata2m note 1 , cnmdata3m note 1 , cnmdata45m note 1 , cnmdata4m note 1 , cnmdata5m note 1 , cnmdata67m note 1 , cnmdata6m note 1 , cnmdata7m note 1 , cnmdlcm note 1 , cnmconfm note 1 , cnmidlm note 1 , cnmidhm note 1 read (8/16 bits) (3 f cpu /f canmod + 1)/(2 + j) (min.) note 2 (4 f cpu /f canmod + 1)/(2 + j) (max.) note 2 crc crcd write 1 number of clocks necessary for access = 3 + i + j + (2 + j) k notes 1. can controller version only 2. digits below the decimal point are rounded up. caution accessing the above register s is prohibited in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock remark f cpu : cpu clock frequency f canmod : can module system clock f can : clock supplied to can i: values (0 or 1) of higher 4 bits of vswc register j: values (0 or 1) of lower 4 bits of vswc register chapter 3 cpu function user?s manual u19201ej3v0ud 132 (3) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an in terrupt request before the instruction in <1> is complete, the execution result of the instru ction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 user?s manual u19201ej3v0ud 133 chapter 4 port functions 4.1 features 4.1.1 v850e/sj3-h i/o ports: 128 ? 5 v tolerant/n-ch open-drain output switch able: 60 (ports 0, 3 to 6, 8, 9) input/output specifiable in 1-bit units 4.1.2 v850e/sk3-h i/o ports: 156 ? 5 v tolerant/n-ch open-drain output switchab le: 78 (ports 0, 2 to 6, 8, 9, 15) input/output specifiable in 1-bit units chapter 4 port functions user?s manual u19201ej3v0ud 134 4.2 basic port configuration 4.2.1 v850e/sj3-h the v850e/sj3-h features a total of 128 i/o ports consisting of ports 0, 1, 3 to 9, cd, cm, cs, ct, dh, and dl. the port configuration is shown below. figure 4-1. port configuration diagram p00 p06 pcd0 pcd3 pcm0 pcm5 pcs0 pcs7 pct0 pct7 pdh0 pdh7 pdl0 pdl15 p30 p39 p40 p42 p50 p55 p60 p615 p10 p11 p80 p81 p70 p715 p90 p915 port 0 port cd port cm port cs port ct port 9 port dh port dl port 3 port 1 port 4 port 5 port 6 port 7 port 8 caution ports 0, 3 to 6, 8, and 9 are 5 v tolerant. table 4-1. i/o buffer power supplies for pins power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports cd, cm, cs, ct, dh, dl ev dd reset, ports 0, 3 to 6, 8, 9 chapter 4 port functions user?s manual u19201ej3v0ud 135 4.2.2 v850e/sk3-h the v850e/sk3-h features a total of 156 i/o ports consisting of ports 0 to 9, 13 to 15, cd, cm, cs, ct, dh, and dl. the port configuration is shown below. figure 4-2. port configuration diagram p00 p06 pcd0 pcd3 pcm0 pcm5 pcs0 pcs7 pct0 pct7 p140 p145 p130 p133 pdh0 pdh7 pdl0 pdl15 p30 p312 p40 p45 p50 p57 p60 p615 p10 p11 p70 p715 p80 p85 p150 p153 p90 p915 p20 p21 port 0 port cd port cm port cs port ct port 9 port dh port dl port 3 port 1 port 4 port 5 port 6 port 7 port 8 port 2 port 13 port 14 port 15 caution ports 0, 2 to 6, 8, 9, and 15 are 5 v tolerant. table 4-2. i/o buffer power supplies for pins power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports 13, 14, cd, cm, cs, ct, dh, dl ev dd reset, ports 0, 2 to 6, 8, 9, 15 chapter 4 port functions user?s manual u19201ej3v0ud 136 4.3 port configuration table 4-3. port configuration (v850e/sj3-h) item configuration control register port n mode register (pmn: n = 0, 1, 3 to 9, cd, cm, cs, ct, dh, dl) port n mode control register (pmcn: n = 0, 3 to 6, 8, 9, cd, cm, cs, ct, dh, dl) port n function control register (pfcn: n = 0, 3 to 6, 8, 9, cd) port n function control expansion register (pfcen: n = 0 note , 3, 5, 6, 8, 9) port n function register (pfn: n = 0, 3 to 6, 8, 9) ports i/o: 128 note the pfce0 register is not included in the pd70f3931, 70f3932, and 70f3933. table 4-4. port configuration (v850e/sk3-h) item configuration control register port n mode register (pmn: n = 0 to 9, 13 to 15, cd, cm, cs, ct, dh, dl) port n mode control register (pmcn: n = 0, 2 to 6, 8, 9, 15, cd, cm, cs, ct, dh, dl) port n function control register (pfcn: n = 0, 3 to 6, 8, 9, cd) port n function control expansion register (pfcen: n = 0, 3, 5, 6, 8, 9) port n function register (pfn: n = 0, 2 to 6, 8, 9, 15) ports i/o: 156 (1) port n register (pn) data is input from or output to an external device by writing or reading the pn register. the pn register consists of a port latch that holds output data, and a circ uit that reads the status of pins. each bit of the pn register corresponds to one pin of port n, and can be read or written in 1-bit units. pn7 outputs 0. outputs 1. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h (output latch) r/w data is written to or read from the pn register as follows, regardless of the setting of the pmcn register. table 4-5. writing/reading pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm = 0) data is written to the output latch note . in the port mode (pmcn = 0), the contents of the output latch are output from the pins. the value of the output latch is read. input mode (pmnm = 1) data is written to the output latch. the pin status is not affected note . the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch. chapter 4 port functions user?s manual u19201ej3v0ud 137 (2) port n mode register (pmn) the pmn register specifies the input or output mode of the corresponding port pin. each bit of this register corresponds to one pin of port n, and the input or output mo de can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of input/output mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the pmcn register specifies the port mode or alternate function. each bit of this register corresponds to one pin of port n, and the mode of the por t can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w chapter 4 port functions user?s manual u19201ej3v0ud 138 (4) port n function control register (pfcn) the pfcn register specifies the alternat e function of a port pin to be used if the pin has two alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function (5) port n function control expansion register (pfcen) the pfcen register specifies the alte rnate function of a port pin to be used if the pin has three or more alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 chapter 4 port functions user?s manual u19201ej3v0ud 139 (6) port n function register (pfn) the pfn register specifies normal output or n-ch open-drain output. each bit of this register corresponds to one pin of por t n, and the output mode of the port pin can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit of the pfn register is valid only when the pmnm bit of the pmn register is 0 (when the output mode is specified) in port mode (pmcnm bit = 0). when the pmnm bit is 1 (when the input mode is specified), the set value of the pfn register is invalid. chapter 4 port functions user?s manual u19201ej3v0ud 140 (7) port setting set a port as illustrated below. figure 4-3. setting of each register and pin function pmcn register output mode input mode pmn register ?0? ?1? ?0? ?1? ?0? ?1? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark set the alternate functions in the following sequence. <1> set the pfcn and pfcen registers. <2> set the pfcn register. <3> set the intrn or intfn register (to specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set. chapter 4 port functions user?s manual u19201ej3v0ud 141 4.3.1 port 0 port 0 is a 7-bit port for which i/o settings can be controlled in 1-bit units. port 0 includes the following alternate-function pins. table 4-6. port 0 alternate-function pins pin no. sj3-h sk3-h pin name gj gm alternate-function pin name i/o remark block type p00 6 6 tip61/top61/sda04 note 1 i/o note 3 p01 7 7 tip60/top60/scl04 note 1 i/o note 3 p02 17 19 nmi input l-1 p03 18 20 intp0/adtrg input n-1 p04 19 21 intp1 input l-1 p05 20 22 intp2/drst note 2 input aa-1 p06 21 23 intp3 input selectable as n-ch open-drain output l-1 notes 1. the sda04 and scl04 pins are not included in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). 2. the drst pin is for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/drst pin to low level between when the reset signal of the reset pin is released and when th e ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . 3. product other than pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h): u-16 pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h ), and 70f3933 (v850e/sj3-h): u-4 caution the p00 to p06 pins have hysteresis characteris tics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) (1) port 0 register (p0) 0 outputs 0. outputs 1. p0n 0 1 output data control (in output mode) (n = 0 to 6) p0 p06 p05 p04 p03 p02 p01 p00 after reset: 00h (output latch) r/w address: fffff400h chapter 4 port functions user?s manual u19201ej3v0ud 142 (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 i/o mode control (n = 0 to 6) pm0 pm06 pm05 pm04 pm03 pm02 pm01 pm00 after reset: ffh r/w address: fffff420h (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input/adtrg input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode after reset: 00h r/w address: fffff440h i/o port tip60 input/top60 output/scl04 note i/o pmc01 0 1 specification of p01 pin operation mode i/o port tip61 input/top61 output/sda04 note i/o pmc00 0 1 specification of p00 pin operation mode note the scl04 and sda04 pins are not included in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). caution the p05/intp2/drst pin becomes the drst pin regardless of the value of the pmc05 bit when the ocdm.ocdm0 bit = 1. chapter 4 port functions user?s manual u19201ej3v0ud 143 (4) port 0 function control register (pfc0) pfc0 after reset: 00h r/w address: fffff460h 0 0 0 0 pfc03 0 pfc01 pfc00 remark for details of alternate function specification, see 4.3.1 (6) port 0 alternate function specifications . (5) port 0 function control expansion re gister (pfce0) (not included in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h).) pfce0 after reset: 00h r/w address: fffff700h 0 0 0 0 0 0 pfce01 pfce00 remark for details of alternate function specification, see 4.3.1 (6) port 0 alternate function specifications . (6) port 0 alternate function specifications. pfc03 specification of p 03 pin alternate function 0 intp0 input 1 adtrg input pfce01 pfc01 specification of p01 pin alternate function 0 0 tip60 input 0 1 top60 output 1 0 scl04 note i/o 1 1 setting prohibited pfce00 pfc00 specification of p00 pin alternate function 0 0 tip61 input 0 1 top61 output 1 0 scl04 note i/o 1 1 setting prohibited note the scl04 and sda04 pins are not included in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). chapter 4 port functions user?s manual u19201ej3v0ud 144 (7) port 0 function register (pf0) 0 normal output (cmos output) n-ch open drain output pf0n 0 1 control of normal output or n-ch open-drain output (n = 0 to 6) pf0 pf06 pf05 pf04 pf03 pf02 pf01 pf00 after reset: 00h r/w address: fffffc60h caution to pull up an output pin at ev dd or higher, be sure to set the appropriate pf0n bit to 1. chapter 4 port functions user?s manual u19201ej3v0ud 145 4.3.2 port 1 port 1 is a 2-bit port for which i/o settings can be controlled in 1-bit units. port 1 includes the following alternate-function pins. table 4-7. port 1 alternate-function pins pin no. sj3-h sk3-h pin name gj gm alternate-function pin name i/o remark block type p10 3 3 ano0 output ? a-2 p11 4 4 ano1 output ? a-2 remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) (1) port 1 register (p1) 0 outputs 0 outputs 1 p1n 0 1 output data control (in output mode) (n = 0, 1) p1 0 0 0 0 0 p11 p10 after reset: 00h (output latch) r/w address: fffff402h caution do not read/write the p1 register during d/a conversion (see 15.4.3 cautions). (2) port 1 mode register (pm1) 1 output mode input mode pm1n 0 1 i/o mode control (n = 0, 1) pm1 1 1 1 1 1 pm11 pm10 after reset: ffh r/w address: fffff422h cautions 1. when using p1n as alternate functions (anon pin output), set the pm1n bit to 1. 2. when using one of the pm10 and pm11 pins as an i/o port and the other as a d/a output pin, do so in an appl ication where the port i/o le vel does not change during d/a output. chapter 4 port functions user?s manual u19201ej3v0ud 146 4.3.3 port 2 (v850e/sk3-h only) port 2 is a 2-bit port for which i/o setti ngs can be controlled in 1-bit units. port 2 includes the following alternate-function pins. table 4-8. port 2 alternate-function pins pin no. sj3-h sk3-h pin name gj gm alternate-function pin name i/o remark block type p20 ? 8 sda04 i/o e-3 p21 ? 9 scl04 i/o n-ch open-drain output selectable e-3 caution the p20 and p21 pins have hysteresis characte ristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) (1) port 2 register (p2) 0 outputs 0. outputs 1. p2n 0 1 output data control (in output mode) (n = 0, 1) p2 0 0 0 0 0 p21 p20 after reset: 00h (output latch) r/w address: fffff404h (2) port 2 mode register (pm2) 1 output mode input mode pm2n 0 1 i/o mode control (n = 0, 1) pm2 1 1 1 1 1 pm21 pm20 after reset: ffh r/w address: fffff424h chapter 4 port functions user?s manual u19201ej3v0ud 147 (3) port 2 mode control register (pmc2) 0 pmc2 0 0 0 0 0 pmc21 pmc20 i/o port scl04 i/o pmc21 0 1 specification of p21 pin operation mode i/o port sda04 i/o pmc20 0 1 specification of p20 pin operation mode after reset: 00h r/w address: fffff444h (4) port 2 function register (pf2) pf2 after reset: 00h r/w address: fffffc64h 0 0 0 0 0 0 pf21 pf20 normal output (cmos output) n-ch open-drain output pf2n 0 1 control of normal output or n-ch open-drain output (n = 0, 1) caution to pull up an output pin at ev dd or higher, be sure to set th e appropriate pf2n bit to 1. chapter 4 port functions user?s manual u19201ej3v0ud 148 4.3.4 port 3 port 3 is a 10-bit (v850e/sj3-h) or 13-bit (v850e/sk3-h) port for which i/o settings can be controlled in 1-bit units. port 3 includes the following alternate-function pins. table 4-9. port 3 alternate-function pins pin no. sj3-h sk3-h pin name gj gm alternate-function pin name i/o remark block type p30 25 30 txda0/sob4 output g-2 p31 26 31 rxda0/intp7/sib4 input n-3 p32 27 32 ascka0/sckb4/tip00/top00 i/o u-1 p33 28 33 tip01/top01/ctxd1 note 2 i/o u-2 p34 29 34 tip10/top10/crxd1 note 2 i/o u-3 p35 30 35 tip11/top11 i/o u-4 p36 31 36 ctxd0 note 3 /ietx0 output g-2 p37 32 37 crxd0 note 3 /ierx0 input g-3 p38 35 40 txda2/sda00/sib2 i/o u-17 p39 36 41 rxda2/scl00/sckb2 i/o u-18 p310 note 1 ? 42 sob2 note 1 output u-19 p311 note 1 ? 43 txda2 note 1 output e-2 p312 note 1 ? 44 rxda2 note 1 input selectable as n-ch open-drain output e-1 notes 1. v850e/sk3-h only 2. can controller (2-channel) version only 3. can controller version only caution the p31 to p35, p37 to p39, and p312 pins have hysteresis characteristi cs in the input mode of the alternate-function pin, but do not have th e hysteresis characteristics in the port mode. remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 4 port functions user?s manual u19201ej3v0ud 149 (1) port 3 register (p3) outputs 0. outputs 1. p3n 0 1 output data control (in output mode) p3 (p3h) after reset: 0000h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h 0 0 0 p312 note p311 note p310 note p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 8 9 10 11 12 13 14 15 (p3l) note valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/s j3-h. however, the read value becomes undefined. caution be sure to clea r bits 13 to 15 to ?0?. remarks 1. the p3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the p3 register as the p3h register and the lower 8 bits as the p3l register, p3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p3h register. 3. v850e/sj3-h: n = 0 to 9 v850e/sk3-h: n = 0 to 12 chapter 4 port functions user?s manual u19201ej3v0ud 150 (2) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 i/o mode control 1 1 pm312 note pm311 note pm310 note pm39 pm38 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 8 9 10 11 12 13 14 15 pm3 (pm3h) (pm3l) note valid for the v850e/sk3-h only. be sure to set this bi t to 1 in the v850e/sj3-h. caution be sure to set bits 13 to 15 to ?1?. remarks 1. the pm3 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pm3 register as the pm3h register and the lower 8 bits as the pm3l register, pm3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of t he pm3 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pm3h register. 3. v850e/sj3-h: n = 0 to 9 v850e/sk3-h: n = 0 to 12 chapter 4 port functions user?s manual u19201ej3v0ud 151 (3) port 3 mode control register (pmc3) (1/2) i/o port rxda2 input/scl00 i/o/sckb2 i/o pmc39 0 1 specification of p39 pin operation mode i/o port txda2 output/sda00 i/o/sib2 input pmc38 0 1 specification of p38 pin operation mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 00 0 pmc312 note 1 pmc311 note 1 pmc310 note 1 pmc39 pmc38 8 9 10 11 12 13 14 15 pmc3 (pmc3h) (pmc3l) i/o port tip11 input/top11 output pmc35 0 1 specification of p35 pin operation mode i/o port crxd0 note 3 input/ierx0 input pmc37 0 1 specification of p37 pin operation mode i/o port ctxd0 note 3 output/ietx0 output pmc36 0 1 specification of p36 pin operation mode i/o port rxda2 note 2 input pmc312 note 1 0 1 specification of p312 pin operation mode i/o port txda2 note 2 output pmc311 note 1 0 1 specification of p311 pin operation mode i/o port sob2 note 2 output pmc310 note 1 0 1 specification of p310 pin operation mode notes 1. valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/sj3-h. 2. v850e/sk3-h only 3. can controller version only caution be sure to clea r bits 13 to 15 to ?0?. chapter 4 port functions user?s manual u19201ej3v0ud 152 (2/2) i/o port tip10 input/top10 output/crxd1 note input pmc34 0 1 specification of p34 pin operation mode i/o port tip01 input/top01 output/ctxd1 note output pmc33 0 1 specification of p33 pin operation mode i/o port ascka0 input/sckb4 i/o/tip00 input/top00 output pmc32 0 1 specification of p32 pin operation mode i/o port rxda0 input/intp7 input/sib4 input pmc31 0 1 specification of p31 pin operation mode i/o port txda0 output/sob4 output pmc30 0 1 specification of p30 pin operation mode note can controller (2-channel) version only remarks 1. the pmc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc3 register as the pmc3h register and the lower 8 bits as the pmc3l register, pmc3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc3h register. chapter 4 port functions user?s manual u19201ej3v0ud 153 (4) port 3 function control register (pfc3) after reset: 0000h r/w address: pfc3 fffff466h, pfc3l fffff466h, pfc3l fffff467h 00 00 0 pfc310 note pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfc3 (pfc3h) (pfc3l) note valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/sj3-h. caution be sure to clea r bits 11 to 15 to ?0?. remarks 1. for details of alternate function specification, see 4.3.4 (6) port 3 alternate function specifications . 2. the pfc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc3 register as the pfc3h register and the lower 8 bits as the pfc3l register, pfc3 can be read or written in 8-bit and 1-bit units. 3. to read/write bits 8 to 15 of the pfc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc3h register. (5) port 3 function control expansion register (pfce3) 00 00 0 pfce310 note pfce39 pfce38 0 0 0 pfce34 pfce33 pfce32 0 0 8 9 10 11 12 13 14 15 pfce3 (pfce3h) (pfce3l) after reset: 0000h r/w address: pfce3 fffff706h, pfce3l fffff706h, pfce3h fffff707h note valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/sj3-h. caution be sure to clear bits 0, 1, 5 to 7, and 11 to 15 to ?0?. remark for details of alternate function specification, see 4.3.4 (6) port 3 alternate function specifications . chapter 4 port functions user?s manual u19201ej3v0ud 154 (6) port 3 alternate function specifications pfce310 pfc310 specification of p310 pin alternate function 1 0 sob2 note 1 output other than above setting prohibited pfce39 pfc39 specification of p39 pin alternate function 0 0 rxda2 input 0 1 scl00 i/o 1 0 sckb2 i/o 1 1 setting prohibited pfce38 pfc38 specification of p38 pin alternate function 0 0 txda2 output 0 1 sda00 i/o 1 0 sib2 input 1 1 setting prohibited pfc37 specification of p37 pin alternate function 0 crxd0 note 2 input 1 ierx0 input pfc36 specification of p36 pin alternate function 0 ctxd0 note 2 output 1 ietx0 output pfc35 specification of p35 pin alternate function 0 tip11 input 1 top11 output notes 1. v850e/sk3-h only 2. can controller version only chapter 4 port functions user?s manual u19201ej3v0ud 155 pfce34 pfc34 specification of p34 pin alternate function 0 0 tip10 input 0 1 top10 output 1 0 crxd1 note 1 input 1 1 setting prohibited pfce33 pfc33 specification of p33 pin alternate function 0 0 tip01 input 0 1 top01 output 1 0 ctxd1 note 1 output 1 1 setting prohibited pfce32 pfc32 specification of p32 pin alternate function 0 0 ascka0 input 0 1 sckb4 i/o 1 0 tip00 input 1 1 top00 output pfc31 specification of p31 pin alternate function 0 rxda0 input/intp7 note 2 input 1 sib4 input pfc30 specification of p30 pin alternate function 0 txda0 output 1 sob4 output notes 1. can controller (2-channel) version only 2. the intp7 pin and rxda0 pin are alternate-func tion pins. when using the pin as the rxda0 pin, disable edge detection for the intp7 alternat e-function pin. (clear the intf3.intf31 bit and the intr3.intr31 bit to 0.) when using the pin as the intp7 pin, stop uarta0 reception. (clear the ua0ctl0.ua0rxe bit to 0.) chapter 4 port functions user?s manual u19201ej3v0ud 156 (7) port 3 function register (pf3) after reset: 0000h r/w address: pf3 fffffc66h, pf3l fffffc66h, pf3h fffffc67h pf37 pf36 pf35 pf34 pf33 pf32 pf31 pf30 0 0 0 pf312 note pf311 note pf310 note pf39 pf38 8 9 10 11 12 13 14 15 normal output (cmos output) n-ch open-drain output pf3n 0 1 control of normal output or n-ch open-drain output pf3 (pf3h) (pf3l) note valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/sj3-h. cautions 1. to pull up an output pin at ev dd or higher, be sure to set the appropriate pf3n bit to 1. 2. be sure to clear bits 13 to 15 to ?0?. remarks 1. the pf3 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pf3 register as the pf3h register and the lower 8 bits as the pf3l register, pf3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of th e pf3 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pf3h register. 3. v850e/sj3-h: n = 0 to 9 v850e/sk3-h: n = 0 to 12 chapter 4 port functions user?s manual u19201ej3v0ud 157 4.3.5 port 4 port 4 is a 3-bit (v850e/sj3-h) or 6-bit (v850e/ sk3-h) port that controls i/o in 1-bit units. port 4 includes the following alternate-function pins. table 4-10. port 4 alternate-function pins pin no. sj3-h sk3-h pin name gj gm alternate-function pin name i/o remark block type p40 22 24 sib0/sda01 i/o g-5 p41 23 25 sob0/scl01 i/o g-6 p42 24 26 sckb0/intp2 i/o n-4 p43 note ? 27 ? ? c-1 p44 note ? 28 ietx0 note output e-2 p45 note ? 29 ierx0 note input selectable as n-ch open-drain output e-1 note v850e/sk3-h only caution the p40 to p42 and 45 pins have hysteresis character istics in the input mode of the alternate- function pin, but do not have the hyster esis characteristics in the port mode. remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 4 port functions user?s manual u19201ej3v0ud 158 (1) port 4 register (p4) 0 outputs 0. outputs 1. p4n 0 1 output data control (in output mode) p4 0 p45 note p44 note p43 note p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h note valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/s j3-h. however, the read value becomes undefined. caution be sure to clear bits 6 and 7 to ?0?. remark v850e/sj3-h: n = 0 to 2 v850e/sk3-h: n = 0 to 5 (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 i/o mode control pm4 1 pm45 note pm44 note pm43 note pm42 pm41 pm40 after reset: ffh r/w address: fffff428h note valid for the v850e/sk3-h only. be sure to set this bi t to 1 in the v850e/sj3-h. caution be sure to set bits 6 and 7 to ?1?. remark v850e/sj3-h: n = 0 to 2 v850e/sk3-h: n = 0 to 5 chapter 4 port functions user?s manual u19201ej3v0ud 159 (3) port 4 mode control register (pmc4) 0 pmc4 0 pmc45 note 1 pmc44 note 1 0 pmc42 pmc41 pmc40 i/o port sckb0 i/o/intp2 input pmc42 0 1 specification of p42 pin operation mode i/o port sob0 output/scl01 i/o pmc41 0 1 specification of p41 pin operation mode i/o port sib0 input/sda01 i/o pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h i/o port ierx0 note 2 input pmc45 note 1 0 1 specification of p45 pin operation mode i/o port ierx0 note 2 output pmc44 note 1 0 1 specification of p44 pin operation mode notes 1. valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/sj3-h. 2. v850e/sk3-h only caution be sure to clear bi ts 3, 6, and 7 to ?0?. chapter 4 port functions user?s manual u19201ej3v0ud 160 (4) port 4 function control register (pfc4) pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 pfc42 pfc41 pfc40 sob0 output scl01 i/o pfc41 0 1 specification of p41 pin alternate function sib0 input sda01 i/o pfc40 0 1 specification of p40 pin alternate function sckb0 i/o intp2 input pfc42 0 1 specification of p42 pin alternate function caution be sure to clea r bits 3 to 7 to ?0?. (5) port 4 function register (pf4) 0 normal output (cmos output) n-ch open-drain output pf4n 0 1 control of normal output or n-ch open-drain output pf4 0 pf45 note pf44 note pf43 note pf42 pf41 pf40 after reset: 00h r/w address: fffffc68h note valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/sj3-h. cautions 1. to pull up an output pin at ev dd or higher, be sure to set the appropriate pf4n bit to 1. 2. be sure to clear bits 6 and 7 to ?0?. remark v850e/sj3-h: n = 0 to 2 v850e/sk3-h: n = 0 to 5 chapter 4 port functions user?s manual u19201ej3v0ud 161 4.3.6 port 5 port 5 is a 6-bit (v850e/sj3-h) or 8-bit (v850e/ sk3-h) port that controls i/o in 1-bit units. port 5 includes the following alternate-function pins. table 4-11. port 5 alternate-function pins pin no. sj3-h sk3-h pin name gj gm alternate-function pin name i/o remark block type p50 37 45 kr0/tiq01/toq01/rtp00 i/o u-5 p51 38 46 intp7/kr1/tiq02/toq02/rtp01 i/o u-20 p52 39 47 kr2/tiq03/toq03/rtp02/ddi note 1 i/o u-6 p53 40 48 sib2/kr3/tiq00/toq00/rtp03/ddo note 1 i/o u-7 p54 41 49 sob2/kr4/rtp04/dck note 1 i/o u-8 p55 42 50 sckb2/kr5/rtp05/dms note 1 i/o u-9 p56 note 2 ? 51 rxda4 note 2 input e-1 p57 note 2 ? 52 txda4 note 2 output selectable as n-ch open-drain output e-2 notes 1. the ddi, ddo, dck, and dms pins are for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/drst pin to low level between when the reset signal of the reset pin is released and when th e ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . 2. v850e/sk3-h only cautions 1. when the power is turned on, the p53 pin may momentarily output an undefined level. 2. the p50 to p56 pins have hysteresis charact eristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 4 port functions user?s manual u19201ej3v0ud 162 (1) port 5 register (p5) p57 note outputs 0. outputs 1. p5n 0 1 output data control (in output mode) p5 p56 note p55 p54 p53 p52 p51 p50 after reset: 00h (output latch) r/w address: fffff40ah note valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/s j3-h. however, the read value becomes undefined. remark v850e/sj3-h: n = 0 to 5 v850e/sk3-h: n = 0 to 7 (2) port 5 mode register (pm5) pm57 note output mode input mode pm5n 0 1 i/o mode control pm5 pm56 note pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah note valid for the v850e/sk3-h only. be sure to set this bi t to 1 in the v850e/sj3-h. remark v850e/sj3-h: n = 0 to 5 v850e/sk3-h: n = 0 to 7 chapter 4 port functions user?s manual u19201ej3v0ud 163 (3) port 5 mode control register (pmc5) pmc57 note 1 pmc5 pmc56 note 1 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 i/o port sckb2 i/o/kr5 input/rtp05 output pmc55 0 1 specification of p55 pin operation mode i/o port sob2 output/kr4 input/rtp04 output pmc54 0 1 specification of p54 pin operation mode i/o port sib2 input/kr3 input/tiq00 input/toq00 output/rtp03 output pmc53 0 1 specification of p53 pin operation mode i/o port kr2 input/tiq03 input/toq03 output/rtp02 output pmc52 0 1 specification of p52 pin operation mode i/o port intp7 input/kr1 input/tiq02 input/toq02 output/rtp01 output pmc51 0 1 specification of p51 pin operation mode i/o port kr0 input/tiq01 input/toq01 output/rtp00 output pmc50 0 1 specification of p50 pin operation mode after reset: 00h r/w address: fffff44ah i/o port txda4 note 2 output pmc57 note 1 0 1 specification of p57 pin operation mode i/o port rxda4 note 2 input pmc56 note 1 0 1 specification of p56 pin operation mode notes 1. valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/sj3-h. 2. v850e/sk3-h only chapter 4 port functions user?s manual u19201ej3v0ud 164 (4) port 5 function control register (pfc5) 0 pfc5 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 after reset: 00h r/w address: fffff46ah remark for details of alternate function specification, see 4.3.6 (6) port 5 alternate function specifications . (5) port 5 function control expansion register (pfce5) 0 pfce5 0 pfce55 pfce54 pfce53 pfce52 pfce51 pfce50 after reset: 00h r/w address: fffff70ah remark for details of alternate function specification, see 4.3.6 (6) port 5 alternate function specifications . (6) port 5 alternate function specifications pfce55 pfc55 specification of p55 pin alternate function 0 0 sckb2 i/o 0 1 kr5 input 1 0 setting prohibited 1 1 rtp05 output pfce54 pfc54 specification of p54 pin alternate function 0 0 sob2 output 0 1 kr4 input 1 0 setting prohibited 1 1 rtp04 output chapter 4 port functions user?s manual u19201ej3v0ud 165 pfce53 pfc53 specification of p53 pin alternate function 0 0 sib2 input 0 1 kr3 note input/tiq00 input 1 0 toq00 output 1 1 rtp03 output pfce52 pfc52 specification of p52 pin alternate function 0 0 setting prohibited 0 1 kr2 note input/tiq03 input 1 0 toq03 input 1 1 rtp02 output pfce51 pfc51 specification of p51 pin alternate function 0 0 intp7 input 0 1 kr1 note input/tiq02 input 1 0 toq02 output 1 1 rtp01 output pfce50 pfc50 specification of p50 pin alternate function 0 0 setting prohibited 0 1 kr0 note input/tiq01 input 1 0 toq01 output 1 1 rtp00 output note the krn pin and tiq0m pin are alternate-function pins. when using the pin as the tiq0m pin, disable krn pin key return detection, which is the al ternate function. (clear the krm.krmn bit to 0.) also, when using the pin as the krn pin, disable tiq0m pin edge detection, which is the alternate function (n = 0 to 3, m = 0 to 3). pin name use as tiq0m pin use as krn pin kr0/tiq01 krm.krm0 bit = 0 tq0ioc1.tq0is3, tq0is2 bits = 00 kr1/tiq02 krm.krm1 bit = 0 tq0ioc1.tq0is5, tq0is4 bits = 00 kr2/tiq03 krm.krm2 bit = 0 tq0ioc1.tq0is7, tq0is6 bits = 00 kr3/tiq00 krm.krm3 bit = 0 tq0ioc1.tq0is1, tq0is0 bits = 00 tq0ioc2.tq0ees1, tq0ees0 bits = 00 tq0ioc2.tq0ets1, tq0ets0 bits = 00 chapter 4 port functions user?s manual u19201ej3v0ud 166 (7) port 5 function register (pf5) pf57 note normal output (cmos output) n-ch open-drain output pf5n 0 1 control of normal output or n-ch open-drain output pf5 pf56 note pf55 pf54 pf53 pf52 pf51 pf50 after reset: 00h r/w address: fffffc6ah note valid for the v850e/sk3-h only. be sure to clear this bit to 0 in the v850e/sj3-h. caution to pull up an output pin at ev dd or higher, be sure to set th e appropriate pf5n bit to 1. remark v850e/sj3-h: n = 0 to 5 v850e/sk3-h: n = 0 to 7 chapter 4 port functions user?s manual u19201ej3v0ud 167 4.3.7 port 6 port 6 is a 16-bit port for which i/o settings can be controlled in 1-bit units. port 6 includes the following alternate-function pins. table 4-12. port 6 alternate-function pins pin no. sj3-h sk3-h pin name gj gm alternate-function pin name i/o remark block type p60 43 53 rtp10/rxda4/sie0 note 1 i/o note 2 p61 44 54 rtp11/txda4/soe0 note 1 output note 2 p62 45 55 rtp12/scke0 note 1 i/o note 2 p63 46 56 rtp13/sie1 note 1 /kr4 i/o note 2 p64 47 57 rtp14/soe1 note 1 /kr5 i/o note 2 p65 48 58 rtp15/scke1 note 1 /kr2/tiq03/toq03 i/o note 2 p66 49 59 sib5/intp9/kr3/tiq00/toq00 i/o u-26 p67 50 60 sob5/rxda5/sda05 note 1 i/o note 2 p68 51 61 sckb5/txda5/scl05 note 1 i/o note 2 p69 52 62 tip70/top70/tenc70 i/o u-29 p610 53 63 tip71/tenc71 input u-30 p611 54 64 top71/tecr7 i/o u-31 p612 55 65 tip80/top80/tenc80 i/o u-29 p613 56 66 tip81/top81/tenc81 i/o u-29 p614 57 67 sda03/tecr8 i/o u-32 p615 58 68 scl03 i/o selectable as n-ch open-drain output e-3 notes 1. these pins are not included in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). 2. block types differ for each product. ? products other than pd70f3931 (v850e/sj3-h), 70f39 32 (v850e/sj3-h), and 70f3933 (v850e/sj3-h) pin name p60 p61 p62 p63 p64 p65 p67 p68 block type u-21 u-22 u-38 u-23 u-24 u-25 u-27 u-28 ? pd70f3931 (v850e/sj3-h), 70f3932 (v850e /sj3-h), and 70f3933 (v850e/sj3-h) pin name p60 p61 p62 p63 p64 p65 p67 p68 block type g-1 g-2 e-2 u-36 u-36 u-37 g-1 g-7 caution the p60 and p62 to p615 pins have hysteresis characteristics in the input mode of the alternate- function pin, but do not have the hyster esis characteristics in the port mode. remark sj3-h: v850e/sj3-h sk3-h: v850e/sk3-h gj (v850e/sj3-h): 144-pin plastic lqfp (fine pitch) (20 20) gm (v850e/sk3-h): 176-pin plastic lqfp (fine pitch) (24 24) chapter 4 port functions user?s manual u19201ej3v0ud 168 (1) port 6 register (p6) p615 outputs 0. outputs 1. p6n 0 1 output data control (in output mode) (n = 0 to 15) p6 (p6h) (p6l) p614 p613 p612 p611 p610 p69 p68 after reset: 0000h (output latch) r/w address: p6 fffff40ch p6l fffff40ch, p6lh fffff40dh p67 p66 p65 p64 p63 p62 p61 p60 8 9 10 11 12 13 14 15 remarks 1. the p6 register can be read or written in 16-bit units. however, when using the higher 8 bits of the p6 register as the p6h register and the lower 8 bits as the p6l register, p6 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p6 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p6h register. (2) port 6 mode register (pm6) pm67 output mode input mode pm6n 0 1 i/o mode control (n = 0 to 15) pm66 pm65 pm64 pm63 pm62 pm61 pm60 after reset: ffffh r/w address: pm6 fffff42ch pm6l fffff42ch, pm6h fffff42dh pm615 pm6 (pm6h) (pm6l) pm614 pm613 pm612 pm611 pm610 pm69 pm68 8 9 10 11 12 13 14 15 remarks 1. the pm6 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pm6 register as the pm6h register and the lower 8 bits as the pm6l register, pm6 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of t he pm6 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pm6h register. chapter 4 port functions user?s manual u19201ej3v0ud 169 (3) port 6 mode control register (pmc6) (1/2) i/o port tip81 input/top81 output/tenc81 input pmc613 0 1 specification of p613 pin operation mode pmc67 pmc66 pmc65 pmc64 pmc63 pmc62 pmc61 pmc60 after reset: 0000h r/w address: pmc6 fffff44ch pmc6l fffff44ch, pmc6h fffff44dh pmc615 pmc6 (pmc6h) (pmc6l) pmc614 pmc613 pmc612 pmc611 pmc610 pmc69 pmc68 8 9 10 11 12 13 14 15 i/o port tip80 input/top80 output/tenc80 input pmc612 0 1 specification of p612 pin operation mode i/o port tip70 input/top70 output/tenc70 input pmc69 0 1 specification of p69 pin operation mode i/o port sckb5 i/o/txda5 output/scl05 note i/o pmc68 0 1 specification of p68 pin operation mode i/o port sob5 output/rxda5 input/sda05 note i/o pmc67 0 1 specification of p67 pin operation mode i/o port top71 output/tecr7 input pmc611 0 1 specification of p611 pin operation mode i/o port scl03 i/o pmc615 0 1 specification of p615 pin operation mode i/o port sda03 i/o/tecr8 input pmc614 0 1 specification of p614 pin operation mode i/o port tip71 input/tenc71 input pmc610 0 1 specification of p610 pin operation mode i/o port sib5 input/intp9 input/kr3 input/tiq00 input/toq00 output pmc66 0 1 specification of p66 pin operation mode i/o port rtp15 output/scke1 note i/o/kr2 input/tiq03 input/toq03 output pmc65 0 1 specification of p65 pin operation mode note not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). chapter 4 port functions user?s manual u19201ej3v0ud 170 (2/2) i/o port rtp14 output/soe1 note output/kr5 input pmc64 0 1 specification of p64 pin operation mode i/o port rtp13 output/sie1 note input/kr4 input pmc63 0 1 specification of p63 pin operation mode i/o port rtp12 output/scke0 note i/o pmc62 0 1 specification of p62 pin operation mode i/o port rtp11 output/txda4 output/soe0 note output pmc61 0 1 specification of p61 pin operation mode i/o port rtp10 output/rxda4 input/sie0 note input pmc60 0 1 specification of p60 pin operation mode note not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). remarks 1. the pmc6 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc6 register as the pmc6h register and the lower 8 bits as the pmc6l register, pmc6 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc6 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc6h register. chapter 4 port functions user?s manual u19201ej3v0ud 171 (4) port 6 function control register (pfc6) 0 pfc614 pfc613 pfc612 pfc611 pfc61 0 pfc69 pfc68 pfc67 pfc66 pfc65 pfc64 pfc63 pfc62 note pfc61 pfc60 8 9 10 11 12 13 14 15 pfc6 (pfc6h) (pfc6l) after reset: 0000h r/w address: pfc6 fffff46ch, pfc6l fffff46ch, pfc6h fffff46dh note not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). be sure to clear this bit to 0 in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). caution be sure to clear bit 15 to ?0?. remarks 1. for details of alternate function specification, see 4.3.7 (6) port 6 alternate function specifications . 2. the pfc6 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc6 register as the pfc6h register and the lower 8 bits as the pfc6l register, pfc6 c an be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfc6 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc6h register. (5) port 6 function control expansion register (pfce6) 0 pfce614 pfce613 pfce612 pfce611 pfce610 pfce69 pfce68 note pfce67 note pfce66 pfce65 pfce64 pfce63 pfce62 note pfce61 note pfce60 note 8 9 10 11 12 13 14 15 pfce6 (pfce6h) (pfce6l) after reset: 0000h r/w address: pfce6 fffff70ch, pfce6l fffff70ch, pfce6h fffff70dh note not available in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). be sure to clear this bit to 0 in the pd70f3931 (v850e/sj3-h), 70f3932 (v850e/sj3-h), and 70f3933 (v850e/sj3-h). caution be sure to clear bit 15 to ?0?. remark for details of alternate function specification, see 4.3.7 (6) port 6 alternate function specifications . chapter 4 port functions user?s manual u19201ej3v0ud 172 (6) port 6 alternate function specifications pfce614 pfc614 specification of p614 pin alternate function 0 0 sda03 i/o 0 1 setting prohibited 1 0 tecr8 input 1 1 setting prohibited pfce613 pfc613 specification of p613 pin alternate function 0 0 tip81 input 0 1 top81 output 1 0 tenc81 input 1 1 setting prohibited pfce612 pfc612 specification of p612 pin alternate function 0 0 tip80 input 0 1 top80 output 1 0 tenc80 input 1 1 setting prohibited pfce611 pfc611 specification of p611 pin alternate function 0 0 top71 output 0 1 setting prohibited 1 0 tecr7 input 1 1 setting prohibited pfce610 pfc610 specification of p610 pin alternate function 0 0 tip71 input 0 1 setting prohibited 1 0 tenc71 input 1 1 setting prohibited pfce69 pfc69 specification of p69 pin alternate function 0 0 tip70 input 0 1 top70 output 1 0 tenc70 input 1 1 setting prohibited pfce68 note 1 pfc68 specification of p68 pin alternate function 0 0 sckb5 i/o 0 1 txda5 output 1 0 scl05 note 2 i/o 1 1 setting prohibited chapter 4 port functions user?s manual u19201ej3v0ud 173 pfce67 note 1 pfc67 specification of p67 pin alternate function 0 0 sob5 output 0 1 rxda5 input 1 0 sda05 note 2 i/o 1 1 setting prohibited pfce66 pfc66 specification of p66 pin alternate function 0 0 sib5 input 0 1 intp9 input 1 0 kr3 note 3 input/tiq00 input 1 1 toq00 output pfce65 pfc65 specification of p65 pin alternate function 0 0 rtp15 output 0 1 scke1 note 2 i/o 1 0 kr2 note 3 input/tiq03 input 1 1 toq03 output pfce64 pfc64 specification of p64 pin alternate function 0 0 rtp14 output 0 1 soe1 note 2 output 1 0 kr5 input 1 1 setting prohibited pfce63 pfc63 specification of p63 pin alternate function 0 0 rtp13 output 0 1 sie1 note 2 input 1 0 kr4 input 1 1 setting prohibited pfce62 note 1 pfc62 note 1 specification of p62 pin alternate function 0 0 rtp12 output 0 1 setting prohibited 1 0 scke0 note 2 i/o 1 1 setting prohibited pfce61 note 1 pfc61 specification of p61 pin alternate function 0 0 rtp11 output 0 1 txda4 output 1 0 soe0 note 2 output 1 1 setting prohibited |